0726198776
There is an issue on the SHI hardware peripheral to detect CS rising/failing with bits CSnFE/CSnRE in the EVSTAT2 register in npcx9m7fb chip. This commit workarounds it by using MIWU to detect the CS rising and failing. Signed-off-by: Tom Chang <CHChang19@nuvoton.com> Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
121 lines
3.5 KiB
Plaintext
121 lines
3.5 KiB
Plaintext
# Host Command backend configs
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# Copyright (c) 2020 Google LLC
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# SPDX-License-Identifier: Apache-2.0
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DT_CHOSEN_ESPI_BACKEND := zephyr,host-cmd-espi-backend
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DT_CHOSEN_SHI_BACKEND := zephyr,host-cmd-shi-backend
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DT_CHOSEN_UART_BACKEND := zephyr,host-cmd-uart-backend
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DT_CHOSEN_SPI_BACKEND := zephyr,host-cmd-spi-backend
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config EC_HOST_CMD_BACKEND_SIMULATOR
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bool "Embedded Controller Host Command Backend Simulator"
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depends on SOC_POSIX
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help
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Enable the EC host command simulator.
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config EC_HOST_CMD_BACKEND_ESPI
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bool "Host commands support using eSPI bus"
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default $(dt_chosen_enabled,$(DT_CHOSEN_ESPI_BACKEND))
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depends on ESPI_PERIPHERAL_EC_HOST_CMD
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depends on ESPI_PERIPHERAL_CUSTOM_OPCODE
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help
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Enable support for Embedded Controller host commands using
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the eSPI bus.
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config EC_HOST_CMD_BACKEND_SHI
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bool "Host commands support using SHI"
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default $(dt_chosen_enabled,$(DT_CHOSEN_SHI_BACKEND))
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help
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Enable support for Embedded Controller host commands using
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the Serial Host Interface.
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config EC_HOST_CMD_BACKEND_UART
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bool "Host commands support using UART"
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default $(dt_chosen_enabled,$(DT_CHOSEN_UART_BACKEND))
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depends on UART_ASYNC_API
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help
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Enable support for Embedded Controller host commands using
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the UART.
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config EC_HOST_CMD_BACKEND_SPI
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bool "Host commands support using SPI"
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help
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Enable support for Embedded Controller host commands using
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the SPI.
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if EC_HOST_CMD_BACKEND_SHI
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choice EC_HOST_CMD_BACKEND_SHI_DRIVER
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prompt "SHI driver"
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default EC_HOST_CMD_BACKEND_SHI_NPCX if SOC_FAMILY_NPCX
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default EC_HOST_CMD_BACKEND_SHI_ITE if SOC_IT8XXX2
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config EC_HOST_CMD_BACKEND_SHI_NPCX
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bool "SHI by Nuvoton"
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depends on DT_HAS_NUVOTON_NPCX_SHI_ENABLED || \
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DT_HAS_NUVOTON_NPCX_SHI_ENHANCED_ENABLED
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help
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This option enables the driver for SHI backend in the
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Nuvoton NPCX chip.
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config EC_HOST_CMD_BACKEND_SHI_ITE
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bool "SHI by ITE"
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depends on DT_HAS_ITE_IT8XXX2_SHI_ENABLED
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help
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This option enables the driver for SHI backend in the
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ITE IT8xxx2 chips family.
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endchoice
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config EC_HOST_CMD_BACKEND_SHI_NPCX_ENHANCED_BUF_MODE
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def_bool DT_HAS_NUVOTON_NPCX_SHI_ENHANCED_ENABLED
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help
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In this mode, besides the original 128-bytes FIFO, an additional
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single-byte output buffer can be selected/switched to generate a
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response to simultaneous Read/Write transactions.
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config EC_HOST_CMD_BACKEND_SHI_NPCX_CS_DETECT_WORKAROUND
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bool
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default y if SOC_NPCX9M7FB
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help
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Workaround the issue "CSnFE and CSnRE bits of EVSTATS2 Register (SHI)"
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in the npcx9m7fb SoC errata.
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config EC_HOST_CMD_BACKEND_SHI_MAX_REQUEST
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int "Max data size for the version 3 request packet"
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default 544 if EC_HOST_CMD_BACKEND_SHI_NPCX
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default 256 if EC_HOST_CMD_BACKEND_SHI_ITE
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help
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This option indicates maximum data size for a version 3 request
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packet. This must be big enough to handle the biggest possible
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request.
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config EC_HOST_CMD_BACKEND_SHI_MAX_RESPONSE
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int "Max data size for the version 3 response packet"
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default 544 if EC_HOST_CMD_BACKEND_SHI_NPCX
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default 248 if EC_HOST_CMD_BACKEND_SHI_ITE
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help
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This option indicates maximum data size for a version 3 response
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packet. This must be big enough to handle the biggest possible
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response.
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endif # EC_HOST_CMD_BACKEND_SHI
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if EC_HOST_CMD_BACKEND_SPI
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choice EC_HOST_CMD_BACKEND_SPI_DRIVER
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prompt "SHI driver"
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default EC_HOST_CMD_BACKEND_SPI_STM32 if DT_HAS_ST_STM32_SPI_HOST_CMD_ENABLED
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config EC_HOST_CMD_BACKEND_SPI_STM32
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bool "SPI by STM32"
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select PINCTRL
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help
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This option enables the driver for SPI backend in the
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STM32 chip family.
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endchoice
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endif # EC_HOST_CMD_BACKEND_SPI
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