9637b8b0bc
This commit adds definition of ACE 3.0 Panther Lake board. Signed-off-by: Anas Nashif <anas.nashif@intel.com> Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
58 lines
1.6 KiB
C
58 lines
1.6 KiB
C
/* Copyright (c) 2021 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _ZEPHYR_SOC_INTEL_ADSP_VECTORS
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#define _ZEPHYR_SOC_INTEL_ADSP_VECTORS
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#include <xtensa/config/core-isa.h>
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/* This is the base address of all the vectors defined in SRAM */
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#define VECBASE_RESET_PADDR_SRAM \
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(L2_SRAM_BASE + CONFIG_HP_SRAM_RESERVE)
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#define MEM_VECBASE_LIT_SIZE 0x178
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/* The addresses of the vectors in SRAM.
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* Only the memerror vector continues to point to its ROM address.
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*/
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#define INTLEVEL2_VECTOR_PADDR_SRAM \
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(VECBASE_RESET_PADDR_SRAM + XCHAL_INTLEVEL2_VECOFS)
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#define INTLEVEL3_VECTOR_PADDR_SRAM \
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(VECBASE_RESET_PADDR_SRAM + XCHAL_INTLEVEL3_VECOFS)
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#define INTLEVEL4_VECTOR_PADDR_SRAM \
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(VECBASE_RESET_PADDR_SRAM + XCHAL_INTLEVEL4_VECOFS)
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#ifndef SOC_SERIES_INTEL_ADSP_ACE
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#define INTLEVEL5_VECTOR_PADDR_SRAM \
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(VECBASE_RESET_PADDR_SRAM + XCHAL_INTLEVEL5_VECOFS)
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#define INTLEVEL6_VECTOR_PADDR_SRAM \
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(VECBASE_RESET_PADDR_SRAM + XCHAL_INTLEVEL6_VECOFS)
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#endif /* SOC_SERIES_INTEL_ADSP_ACE */
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#define INTLEVEL7_VECTOR_PADDR_SRAM \
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(VECBASE_RESET_PADDR_SRAM + XCHAL_NMI_VECOFS)
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#define KERNEL_VECTOR_PADDR_SRAM \
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(VECBASE_RESET_PADDR_SRAM + XCHAL_KERNEL_VECOFS)
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#define USER_VECTOR_PADDR_SRAM \
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(VECBASE_RESET_PADDR_SRAM + XCHAL_USER_VECOFS)
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#define DOUBLEEXC_VECTOR_PADDR_SRAM \
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(VECBASE_RESET_PADDR_SRAM + XCHAL_DOUBLEEXC_VECOFS)
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#define VECTOR_TBL_SIZE 0x1000
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/* Vector and literal sizes */
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#define MEM_VECT_LIT_SIZE 0x8
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#define MEM_VECT_TEXT_SIZE 0x38
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#define MEM_ERROR_TEXT_SIZE 0x180
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#define MEM_ERROR_LIT_SIZE 0x8
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#endif /* _ZEPHYR_SOC_INTEL_ADSP_VECTORS */
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