Peter Ujfalusi 85758444f7 intel_adsp: clk: Configure correct cardinal clock divider for PTL ... The Audio integration PLL is faster on PTL compared to earlier ACE platforms: 442.368 MHz instead 393.216 MHz, however the default divider remained 16, which will result incorrect cardinal clock speed. Change the divider to 18 in order to get correct 24.576 MHz cardinal clock. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>		2024-08-20 10:33:04 +02:00
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ace15_mtpm	soc: intel_adsp: Avoid duplicate adsp_memory_regions	2024-06-07 09:52:42 +02:00
ace20_lnl	soc: intel_adsp: Avoid duplicate adsp_memory_regions	2024-06-07 09:52:42 +02:00
ace30_ptl	intel_adsp: clk: Configure correct cardinal clock divider for PTL	2024-08-20 10:33:04 +02:00
adsp_imr_layout.h	everywhere: replace double words	2024-06-22 05:40:22 -04:00
adsp_memory_regions.h	soc: intel_adsp: Avoid duplicate adsp_memory_regions	2024-06-07 09:52:42 +02:00
adsp_memory.h	intel: adsp: fix firmware image in IMR overwriting	2024-07-27 10:42:27 +03:00
adsp_timestamp.h
dmic_regs.h	intel_adsp: dmic: enable support for ptl use new headers	2024-06-04 13:40:04 +02:00