de82190e13
remove litex,sys-clock-frequency from litex,clk, because we already define that in the clock-frequency of cpu0. This can be accessed via CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC. Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
89 lines
2.0 KiB
YAML
89 lines
2.0 KiB
YAML
# Copyright (c) 2020 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: Apache-2.0
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include: [clock-controller.yaml, base.yaml]
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description: |
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LiteX Mixed Mode Clock Manager
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Common clock driver with MMCM unit for dynamic reconfiguration
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of up to 7 clock outputs with ability to change frequency, duty
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cycle and phase offset
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compatible: "litex,clk"
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clock-cells:
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- id
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properties:
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reg:
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description: Base address and lengths of the register space
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"#clock-cells":
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required: true
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const: 1
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clock-output-names:
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required: true
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type: string-array
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description: |
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List of strings of clock output signal names indexed
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by the first cell in the clock specifier.
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litex,lock-timeout:
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required: true
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type: int
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description: |
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Number of ms to wait for MMCM to assert LOCK signal
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litex,drdy-timeout:
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required: true
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type: int
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description: |
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Number of ms to wait for MMCM to assert DRDY signal
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litex,divclk-divide-min:
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required: true
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type: int
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description: |
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minimal global divider
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litex,divclk-divide-max:
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required: true
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type: int
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description: |
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maximal global divider
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litex,clkfbout-mult-min:
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required: true
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type: int
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description: |
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minimal global multiplier
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litex,clkfbout-mult-max:
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required: true
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type: int
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description: |
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maximal global multiplier
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litex,vco-freq-min:
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required: true
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type: int
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description: |
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minimal frequency after global divider and multiplier
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litex,vco-freq-max:
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required: true
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type: int
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description: |
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maximal frequency after global divider and multiplier
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litex,clkout-divide-min:
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required: true
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type: int
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description: |
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minimal clock output divider
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litex,clkout-divide-max:
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required: true
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type: int
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description: |
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maximal clock output divider
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litex,vco-margin:
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required: true
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type: int
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description: |
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tolerancy for vco frequency
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const: 0
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