Tom Chang 0726198776 mgmt: ec_host_cmd: npcx: workaround for backend SHI ... There is an issue on the SHI hardware peripheral to detect CS rising/failing with bits CSnFE/CSnRE in the EVSTAT2 register in npcx9m7fb chip. This commit workarounds it by using MIWU to detect the CS rising and failing. Signed-off-by: Tom Chang <CHChang19@nuvoton.com> Signed-off-by: Jun Lin <CHLin56@nuvoton.com>		2024-09-13 09:17:23 +02:00
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npcm	soc: arm: add nuvoton npcm400 support	2024-08-20 10:32:43 +02:00
npcx	dts: npcx: workaroud bbram 1st byte issue for npcx4	2024-06-21 10:07:41 +02:00
m2l31kid.dtsi
m2l31x.dtsi	soc: nuvoton: numaker: add poweroff for m2l31x	2024-08-16 11:20:26 +01:00
m46x.dtsi	drivers: usb: udc: change numaker m46x usbd clock source to hirc48m	2024-08-19 10:00:07 -04:00
m48x.dtsi
npcm400.dtsi	soc: arm: add nuvoton npcm400 support	2024-08-20 10:32:43 +02:00
npcx4m3f.dtsi
npcx4m8f.dtsi
npcx7m6fb.dtsi
npcx7m6fc.dtsi
npcx7m7fc.dtsi
npcx9m3f.dtsi
npcx9m6f.dtsi
npcx9m7f.dtsi
npcx9m7fb.dtsi	mgmt: ec_host_cmd: npcx: workaround for backend SHI	2024-09-13 09:17:23 +02:00
npcx9mfp.dtsi