42396735bf
xtensa is the only architecutre doing thing differently and introduces inconsistency in the init process and dependencies as we attemp to cleanup init levels and remove misused of SYS_INIT. Introduce prep_c for this architecture and align with other architectures. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
195 lines
5.5 KiB
ArmAsm
195 lines
5.5 KiB
ArmAsm
/*
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* Copyright (c) 2016 Cadence Design Systems, Inc.
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* Control arrives here at _start from the reset vector.
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*/
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#include <xtensa/coreasm.h>
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/* Exports */
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.global _start
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/*
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* Imports
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* __stack from linker script (see LSP Ref Manual)
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* _bss_table_start from linker script (see LSP Ref Manual)
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* _bss_table_end from linker script (see LSP Ref Manual)
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* z_cstart Entry point into Zephyr C domain
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* __stack from linker script (see LSP Ref Manual)
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*/
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.global __start
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.type z_prep_c, @function
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/* Macros to abstract away ABI differences */
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#if __XTENSA_CALL0_ABI__
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# define CALL call0
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# define CALLX callx0
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# define ARG1 a2 /* 1st outgoing call argument */
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# define ARG2 a3 /* 2nd outgoing call argument */
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# define ARG3 a4 /* 3rd outgoing call argument */
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# define ARG4 a5 /* 4th outgoing call argument */
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# define ARG5 a6 /* 5th outgoing call argument */
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#else
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# define CALL call4
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# define CALLX callx4
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# define ARG1 a6 /* 1st outgoing call argument */
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# define ARG2 a7 /* 2nd outgoing call argument */
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# define ARG3 a8 /* 3rd outgoing call argument */
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# define ARG4 a9 /* 4th outgoing call argument */
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# define ARG5 a10 /* 5th outgoing call argument */
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#endif
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.text
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.align 4
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_start:
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/*
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* _start is typically NOT at the beginning of the text segment --
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* it is always called from either the reset vector (__start) or other
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* code that does equivalent initialization.
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*
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* Assumptions on entry to _start:
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* - low (level-one) and medium priority interrupts are disabled
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* via PS.INTLEVEL and/or INTENABLE
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* - C calling context not initialized:
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* - PS not initialized
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* - SP not initialized
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* - the following are initialized:
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* - LITBASE, cache attributes, WindowBase, WindowStart,
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* CPENABLE, FP's FCR and FSR, EXCSAVE[n]
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* Keep a0 zero. It is used to initialize a few things.
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* It is also the return address, where zero indicates
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* that the frame used by _start is the bottommost frame.
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*
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*/
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/* not needed for Xtensa TX */
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#if !XCHAL_HAVE_HALT || !XCHAL_HAVE_BOOTLOADER
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movi a0, 0 /* keep this register zero. */
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#endif
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/*
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* Initialize the stack pointer.
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* See the "ABI and Software Conventions" chapter in the
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* Xtensa ISA Reference manual for details.
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*
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* NOTE: Because the _start routine does not use any memory in its
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* stack frame, and because all of its CALL instructions use a
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* window size of 4, the stack frame for _start can be empty.
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*/
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movi sp, __stack
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/*
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* Now that sp (a1) is set, we can set PS as per the application (user
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* vector mode, disable interrupts, enable window exceptions if
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* applicable).
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*/
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#if XCHAL_HAVE_EXCEPTIONS
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# ifdef __XTENSA_CALL0_ABI__
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/*
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* PS.WOE = 0
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* PS.UM = 1
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* PS.EXCM = 0
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* PS.INTLEVEL = XCHAL_EXCM_LEVEL
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*/
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movi a3, PS_UM|PS_INTLEVEL(XCHAL_EXCM_LEVEL)
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# else
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/*
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* PS.WOE = 1
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* PS.UM = 1
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* PS.EXCM = 0
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* PS.INTLEVEL = XCHAL_EXCM_LEVEL
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*/
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movi a3, PS_UM|PS_WOE|PS_INTLEVEL(XCHAL_EXCM_LEVEL)
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# endif
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wsr a3, PS
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rsync
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#endif
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/*
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* Do any initialization that affects the memory map, such as
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* setting up TLB entries, that needs to be done before we can
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* successfully clear BSS (e.g. if some BSS segments are in
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* remapped areas).
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*
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* NOTE: This hook works where the reset vector does not unpack
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* segments (see "ROM packing" in the LSP manual), or where
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* unpacking of segments is not affected by memory remapping.
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* If ROM unpacking is affected, TLB setup must be done in
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* assembler from the reset vector.
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*
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* The __memmap_init() routine can be a C function, however it
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* does not have BSS initialized! In particular, __memmap_init()
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* cannot set BSS variables, i.e. uninitialized global variables
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* (they'll be wiped out by the following BSS clear), nor can it
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* assume they are yet initialized to zero.
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*
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* The __memmap_init() function is optional. It is marked as a
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* weak symbol, so that it gets valued zero if not defined.
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*/
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.weak __memmap_init
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movi a4, __memmap_init
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beqz a4, 1f
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CALLX a4
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1:
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#if !XCHAL_HAVE_BOOTLOADER /* boot loader takes care of zeroing BSS */
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# ifdef __XTENSA_CALL0_ABI__
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/* Clear a0 again as possible CALLX to __memmap_init changed it. */
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movi a0, 0
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# endif
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/*
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* Clear the BSS (uninitialized data) segments.
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* This code supports multiple zeroed sections (*.bss).
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*
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* Register allocation:
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* a0 = 0
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* a6 = pointer to start of table, and through table
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* a7 = pointer to end of table
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* a8 = start address of bytes to be zeroed
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* a9 = end address of bytes to be zeroed
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* a10 = length of bytes to be zeroed
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*/
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movi a6, _bss_table_start
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movi a7, _bss_table_end
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bgeu a6, a7, .L3zte
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.L0zte: l32i a8, a6, 0 /* get start address, assumed multiple of 4 */
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l32i a9, a6, 4 /* get end address, assumed multiple of 4 */
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addi a6, a6, 8 /* next entry */
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sub a10, a9, a8 /* a10 = length, assumed a multiple of 4 */
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bbci.l a10, 2, .L1zte
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s32i a0, a8, 0 /* clear 4 bytes to make len multiple of 8 */
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addi a8, a8, 4
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.L1zte: bbci.l a10, 3, .L2zte
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s32i a0, a8, 0 /* clear 8 bytes to make len multiple of 16 */
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s32i a0, a8, 4
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addi a8, a8, 8
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.L2zte: srli a10, a10, 4 /* len is now multiple of 16, divide by 16 */
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floopnez a10, clearzte
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s32i a0, a8, 0 /* clear 16 bytes at a time... */
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s32i a0, a8, 4
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s32i a0, a8, 8
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s32i a0, a8, 12
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addi a8, a8, 16
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floopend a10, clearzte
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bltu a6, a7, .L0zte /* loop until end of table of *.bss sections */
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.L3zte:
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#endif /* !XCHAL_HAVE_BOOTLOADER */
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/* Enter C domain, never returns from here */
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CALL z_prep_c
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.size _start, . - _start
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