502d306630
The OpenISA RV32M1 SoC has four CPU cores. Two of these are RISC-V 32-bit cores, which are named "RI5CY" and "ZERO-RISCY". (The other two cores are ARM Cortex-M0+ and -M4.) This patch adds basic SoC enablement for the RISC-V cores: - basic dtsi, to be extended as additional drivers are added - SoC definition in soc/riscv32/openisa_rv32m1 for RI5CY / ZERO-RISCY - system timer driver for RI5CY, based on LPTMR0 peripheral The timer driver will be generalized a bit soon once proper multi-level interrupt support is available. Emphasis is on supporting the RI5CY core as the more capable of the two; the ZERO-RISCY SoC definitions are a good starting point, but additional work setting up a dtsi and initial drivers is needed to support that core. Signed-off-by: Marti Bolivar <marti@foundries.io> Signed-off-by: Michael Scott <mike@foundries.io>
42 lines
730 B
Plaintext
42 lines
730 B
Plaintext
# Kconfig - external HAL source code configuration options
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#
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# Copyright (c) 2016-2017 Linaro Ltd.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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# When adding new entries keep the list in alphabetical order
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menu "HALs"
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source "ext/hal/atmel/asf/Kconfig"
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source "ext/hal/altera/Kconfig"
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source "ext/hal/cmsis/Kconfig"
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source "ext/hal/cypress/Kconfig"
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source "ext/hal/libmetal/Kconfig"
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source "ext/hal/nordic/Kconfig"
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source "ext/hal/nxp/mcux/Kconfig"
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source "ext/hal/nxp/imx/Kconfig"
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source "ext/hal/openisa/vega_sdk_riscv/Kconfig"
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source "ext/hal/qmsi/Kconfig"
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source "ext/hal/silabs/gecko/Kconfig"
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source "ext/hal/st/stm32cube/Kconfig"
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source "ext/hal/st/lib/Kconfig"
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source "ext/hal/ti/simplelink/Kconfig"
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endmenu
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