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zephyr/soc/xtensa
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Tomasz Leman 60a20471b5 intel_adsp: ace: enable interrupts for secondary core 
Temporary re-enabling interrupts before going to waiti. Right now
secondary cores don't have proper context restore flow and after leaving
D3 state core will return here and stuck. This is temporary workaround.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2023-02-02 03:29:20 +09:00
..
esp32 driver: clock: esp32: retrieve HW clock from DTS 2023-01-03 17:12:06 -05:00
esp32_net driver: clock: esp32: retrieve HW clock from DTS 2023-01-03 17:12:06 -05:00
esp32s2 driver: clock: esp32: retrieve HW clock from DTS 2023-01-03 17:12:06 -05:00
intel_adsp intel_adsp: ace: enable interrupts for secondary core 2023-02-02 03:29:20 +09:00
nxp_adsp xtensa: linker: Use zephyr's convention for rodata 2022-11-17 15:44:48 +09:00
sample_controller xtensa: linker: Use zephyr's convention for rodata 2022-11-17 15:44:48 +09:00
CMakeLists.txt