Add 'U' to a value when assigning it to an unsigned variable. MISRA-C rule 7.2 Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
362 lines
10 KiB
C
362 lines
10 KiB
C
/*
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* Copyright (c) 2011-2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* @brief load/store portion of FPU sharing test
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*
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* @defgroup kernel_fpsharing_tests FP Sharing Tests
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*
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* @ingroup all_tests
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*
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* @details This module implements the load/store portion of the
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* FPU sharing test. This version of this test utilizes a pair of tasks.
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*
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* The load/store test validates the floating point unit context
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* save/restore mechanism. This test utilizes a pair of threads of different
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* priorities that each use the floating point registers. The context
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* switching that occurs exercises the kernel's ability to properly preserve the
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* floating point registers. The test also exercises the kernel's ability to
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* automatically enable floating point support for a task, if supported.
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*
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* FUTURE IMPROVEMENTS
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* On architectures where the non-integer capabilities are provided in a
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* hierarchy, for example on IA-32 the USE_FP and USE_SSE options are provided,
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* this test should be enhanced to ensure that the architectures' _Swap()
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* routine doesn't context switch more registers that it needs to (which would
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* represent a performance issue). For example, on the IA-32, the test should
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* issue a k_fp_disable() from main(), and then indicate that only x87 FPU
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* registers will be utilized (k_fp_enable()). The thread should continue
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* to load ALL non-integer registers, but main() should validate that only the
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* x87 FPU registers are being saved/restored.
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* @{
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* @}
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*/
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#ifndef CONFIG_FLOAT
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#error Rebuild with the FLOAT config option enabled
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#endif
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#ifndef CONFIG_FP_SHARING
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#error Rebuild with the FP_SHARING config option enabled
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#endif
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#if defined(CONFIG_ISA_IA32)
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#ifndef CONFIG_SSE
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#error Rebuild with the SSE config option enabled
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#endif
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#endif /* CONFIG_ISA_IA32 */
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#include <zephyr.h>
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#if defined(CONFIG_ISA_IA32)
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#if defined(__GNUC__)
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#include "float_regs_x86_gcc.h"
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#else
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#include "float_regs_x86_other.h"
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#endif /* __GNUC__ */
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_FP)
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#if defined(__GNUC__)
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#include "float_regs_arm_gcc.h"
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#else
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#include "float_regs_arm_other.h"
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#endif /* __GNUC__ */
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#endif
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#include <tc_util.h>
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#include "float_context.h"
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#include <stddef.h>
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#include <string.h>
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#define MAX_TESTS 500
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#define STACKSIZE 2048
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#define HI_PRI 5
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#define LO_PRI 10
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/* space for float register load/store area used by low priority task */
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static struct fp_register_set float_reg_set_load;
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static struct fp_register_set float_reg_set_store;
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/* space for float register load/store area used by high priority thread */
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static struct fp_register_set float_reg_set;
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/* flag indicating that an error has occurred */
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int fpu_sharing_error;
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/*
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* Test counters are "volatile" because GCC may not update them properly
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* otherwise. (See description of pi calculation test for more details.)
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*/
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static volatile unsigned int load_store_low_count;
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static volatile unsigned int load_store_high_count;
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extern void calculate_pi_low(void);
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extern void calculate_pi_high(void);
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/**
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*
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* @brief Low priority FPU load/store thread
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*
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* @ingroup kernel_fpsharing_tests
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*
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* @see k_sched_time_slice_set(), memset(),
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* _load_all_float_registers(), _store_all_float_registers()
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*/
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void load_store_low(void)
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{
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unsigned int i;
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unsigned char init_byte;
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unsigned char *store_ptr = (unsigned char *)&float_reg_set_store;
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unsigned char *load_ptr = (unsigned char *)&float_reg_set_load;
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volatile char volatile_stack_var = 0;
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PRINT_DATA("Floating point sharing tests started\n");
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PRINT_LINE;
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/*
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* The high priority thread has a sleep to get this (low pri) thread
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* running and here (low priority) we enable slicing and waste cycles
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* to run hi pri thread in between fp ops.
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*
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* Enable round robin scheduling to allow both the low priority pi
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* computation and load/store tasks to execute. The high priority pi
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* computation and load/store tasks will preempt the low priority tasks
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* periodically.
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*/
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k_sched_time_slice_set(10, LO_PRI);
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/*
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* Initialize floating point load buffer to known values;
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* these values must be different than the value used in other threads.
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*/
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init_byte = MAIN_FLOAT_REG_CHECK_BYTE;
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for (i = 0U; i < SIZEOF_FP_REGISTER_SET; i++) {
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load_ptr[i] = init_byte++;
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}
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/* Keep cranking forever, or until an error is detected. */
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for (load_store_low_count = 0U;; load_store_low_count++) {
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/*
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* Clear store buffer to erase all traces of any previous
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* floating point values that have been saved.
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*/
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(void)memset(&float_reg_set_store, 0, SIZEOF_FP_REGISTER_SET);
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/*
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* Utilize an architecture specific function to load all the
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* floating point registers with known values.
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*/
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_load_all_float_registers(&float_reg_set_load);
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/*
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* Waste some cycles to give the high priority load/store
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* thread an opportunity to run when the low priority thread is
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* using the floating point registers.
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*
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* IMPORTANT: This logic requires that z_tick_get_32() not
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* perform any floating point operations!
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*/
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while ((z_tick_get_32() % 5) != 0) {
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/*
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* Use a volatile variable to prevent compiler
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* optimizing out the spin loop.
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*/
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++volatile_stack_var;
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}
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/*
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* Utilize an architecture specific function to dump the
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* contents of all floating point registers to memory.
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*/
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_store_all_float_registers(&float_reg_set_store);
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/*
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* Compare each byte of buffer to ensure the expected value is
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* present, indicating that the floating point registers weren't
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* impacted by the operation of the high priority thread(s).
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*
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* Display error message and terminate if discrepancies are
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* detected.
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*/
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init_byte = MAIN_FLOAT_REG_CHECK_BYTE;
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for (i = 0U; i < SIZEOF_FP_REGISTER_SET; i++) {
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if (store_ptr[i] != init_byte) {
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TC_ERROR("load_store_low found 0x%x instead "
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"of 0x%x @ offset 0x%x\n",
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store_ptr[i],
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init_byte, i);
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TC_ERROR("Discrepancy found during "
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"iteration %d\n",
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load_store_low_count);
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fpu_sharing_error = 1;
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}
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init_byte++;
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}
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/*
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* Terminate if a test error has been reported.
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*/
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if (fpu_sharing_error) {
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TC_END_RESULT(TC_FAIL);
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TC_END_REPORT(TC_FAIL);
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return;
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}
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#if defined(CONFIG_ISA_IA32)
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/*
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* After every 1000 iterations (arbitrarily chosen), explicitly
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* disable floating point operations for the task. The
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* subsequent execution of _load_all_float_registers() will
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* result in an exception to automatically re-enable
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* floating point support for the task.
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*
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* The purpose of this part of the test is to exercise the
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* k_float_disable() API, and to also continue exercising
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* the (exception based) floating enabling mechanism.
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*/
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if ((load_store_low_count % 1000) == 0) {
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k_float_disable(k_current_get());
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}
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#elif defined(CONFIG_CPU_CORTEX_M4)
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/*
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* The routine k_float_disable() allows for thread-level
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* granularity for disabling floating point. Furthermore, it
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* is useful for testing on the fly thread enabling of floating
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* point. Neither of these capabilities are currently supported
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* for ARM.
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*/
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#endif
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}
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}
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/**
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*
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* @brief High priority FPU load/store thread
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*
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* @ingroup kernel_fpsharing_tests
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*
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* @see _load_then_store_all_float_registers()
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*/
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void load_store_high(void)
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{
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unsigned int i;
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unsigned char init_byte;
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unsigned char *reg_set_ptr = (unsigned char *)&float_reg_set;
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/* test until the specified time limit, or until an error is detected */
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while (1) {
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/*
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* Initialize the float_reg_set structure by treating it as
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* a simple array of bytes (the arrangement and actual number
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* of registers is not important for this generic C code). The
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* structure is initialized by using the byte value specified
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* by the constant FIBER_FLOAT_REG_CHECK_BYTE, and then
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* incrementing the value for each successive location in the
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* float_reg_set structure.
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*
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* The initial byte value, and thus the contents of the entire
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* float_reg_set structure, must be different for each
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* thread to effectively test the kernel's ability to
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* properly save/restore the floating point values during a
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* context switch.
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*/
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init_byte = FIBER_FLOAT_REG_CHECK_BYTE;
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for (i = 0U; i < SIZEOF_FP_REGISTER_SET; i++) {
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reg_set_ptr[i] = init_byte++;
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}
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/*
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* Utilize an architecture specific function to load all the
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* floating point registers with the contents of the
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* float_reg_set structure.
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*
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* The goal of the loading all floating point registers with
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* values that differ from the values used in other threads is
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* to help determine whether the floating point register
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* save/restore mechanism in the kernel's context switcher
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* is operating correctly.
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*
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* When a subsequent k_timer_test() invocation is
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* performed, a (cooperative) context switch back to the
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* preempted task will occur. This context switch should result
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* in restoring the state of the task's floating point
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* registers when the task was swapped out due to the
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* occurrence of the timer tick.
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*/
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_load_then_store_all_float_registers(&float_reg_set);
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/*
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* Relinquish the processor for the remainder of the current
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* system clock tick, so that lower priority threads get a
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* chance to run.
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*
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* This exercises the ability of the kernel to restore the
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* FPU state of a low priority thread _and_ the ability of the
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* kernel to provide a "clean" FPU state to this thread
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* once the sleep ends.
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*/
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k_sleep(1);
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/* periodically issue progress report */
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if ((++load_store_high_count % 100) == 0) {
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PRINT_DATA("Load and store OK after %u (high) "
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"+ %u (low) tests\n",
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load_store_high_count,
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load_store_low_count);
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}
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/* terminate testing if specified limit has been reached */
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if (load_store_high_count == MAX_TESTS) {
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TC_END_RESULT(TC_PASS);
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TC_END_REPORT(TC_PASS);
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return;
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}
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}
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}
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#if defined(CONFIG_ISA_IA32)
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#define THREAD_FP_FLAGS (K_FP_REGS | K_SSE_REGS)
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#else
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#define THREAD_FP_FLAGS (K_FP_REGS)
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#endif
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K_THREAD_DEFINE(load_low, STACKSIZE, load_store_low, NULL, NULL, NULL,
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LO_PRI, THREAD_FP_FLAGS, K_NO_WAIT);
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K_THREAD_DEFINE(load_high, STACKSIZE, load_store_high, NULL, NULL, NULL,
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HI_PRI, THREAD_FP_FLAGS, K_NO_WAIT);
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K_THREAD_DEFINE(pi_low, STACKSIZE, calculate_pi_low, NULL, NULL, NULL,
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LO_PRI, THREAD_FP_FLAGS, K_NO_WAIT);
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K_THREAD_DEFINE(pi_high, STACKSIZE, calculate_pi_high, NULL, NULL, NULL,
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HI_PRI, THREAD_FP_FLAGS, K_NO_WAIT);
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