Jay Vasanth 4495f43dca soc arm: MEC172x soc.h - Include custom IRQn_Type ... Fix for issue #41012 to allow compiler to treat IRQn_Type to be more than 8-bit. This will ensure NVIC numbers more than 127 (required for MEC172x device) will work correctly with irq_enable() API Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>		2022-01-20 13:42:16 -05:00
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arc	soc: arc: fix ARC_HAS_ACCL_REGS settings	2021-12-02 11:32:14 -06:00
arm	soc arm: MEC172x soc.h - Include custom IRQn_Type	2022-01-20 13:42:16 -05:00
arm64	soc: remove unnecessary inclusions of devicetree.h	2022-01-11 11:52:27 +01:00
mips	soc: mips: add Qemu Malta support	2022-01-19 13:48:21 -05:00
nios2	soc: nios2: Cleanup linker scripts to use new DTS macros	2020-04-30 20:59:13 -05:00
posix	posix: Add missing include	2021-04-27 13:17:36 -04:00
riscv	ITE: drivers/bbram: add magic number to compare in initial	2022-01-17 11:52:13 -05:00
sparc	boards: set CPU_HAS_FPU on LEON3 soc and boards	2020-12-04 14:33:43 +02:00
x86	bluetooth: remove Kconfig options CONFIG_BT_*_ON_DEV_NAME	2021-08-25 18:05:17 -04:00
xtensa	arch/xtensa: Use ZSR assignments for the CPU pointer	2022-01-20 12:58:00 -05:00
Kconfig	kconfig: soc and shield cleanup	2021-06-11 16:13:22 +02:00