cce530cae4
Some architectures such as RISC-v support more than 255 interrupts per aggrigator. This diff adds the ability to forgo the aggrigator pattern and use a configurable number of bits for multilevel interruts. Signed-off-by: Joshua Lilly <jgl@meta.com> |
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| .. | ||
| data_passing | ||
| other | ||
| scheduling | ||
| smp | ||
| synchronization | ||
| threads | ||
| timing | ||
| index.rst | ||
| interrupts.rst | ||
| polling.rst | ||