zephyr/soc/intel
Girisha Dengi 36e71c839f drivers: clock_control: Agilex5 clock control driver updates
The clock controller/manager registers are updated with
the correct divider values by bootloader via hand-off
data, so now we can use the clock controller to get the
clock value of each peripheral during the run time.

Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
2024-12-16 17:12:34 -05:00
..
alder_lake
apollo_lake
atom
common
elkhart_lake
intel_adsp Revert "soc: intel_adsp/ace30: do not map 0x0" 2024-11-29 19:27:53 -05:00
intel_ish soc: intel_ish: remove duplicate hook 2024-09-21 11:29:06 +02:00
intel_niosv arch: riscv: introduce CONFIG_RISCV_GP_PURPOSE choice 2024-11-28 12:51:09 +01:00
intel_socfpga drivers: clock_control: Agilex5 clock control driver updates 2024-12-16 17:12:34 -05:00
intel_socfpga_std soc: Remove re-defining some defined types 2024-11-18 07:41:23 -05:00
lakemont
raptor_lake