f54c57effe
GICC_BPR has minimum legal values in secure and non-secure states. '3' is the minimum BPR value leading to group and sub-group priority as 'gggg.ssss'. In order to make an IRQ preemptible they need to be in different priority group. Hence to be generic priority values should be above '0x0f'. IRQ0 - default priority (low prio) IRQ1 - 0x0 (highest prio) Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
98 lines
2.2 KiB
C
98 lines
2.2 KiB
C
/*
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* Copyright (c) 2018 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef INTERRUPT_UTIL_H_
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#define INTERRUPT_UTIL_H_
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#include <ztest.h>
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#define MS_TO_US(ms) (ms * USEC_PER_MSEC)
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#if defined(CONFIG_CPU_CORTEX_M)
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#include <arch/arm/aarch32/cortex_m/cmsis.h>
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static inline uint32_t get_available_nvic_line(uint32_t initial_offset)
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{
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int i;
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for (i = initial_offset - 1; i >= 0; i--) {
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if (NVIC_GetEnableIRQ(i) == 0) {
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/*
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* Interrupts configured statically with IRQ_CONNECT(.)
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* are automatically enabled. NVIC_GetEnableIRQ()
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* returning false, here, implies that the IRQ line is
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* either not implemented or it is not enabled, thus,
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* currently not in use by Zephyr.
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*/
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/* Set the NVIC line to pending. */
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NVIC_SetPendingIRQ(i);
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if (NVIC_GetPendingIRQ(i)) {
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/*
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* If the NVIC line is pending, it is
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* guaranteed that it is implemented; clear the
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* line and return the NVIC line number.
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*/
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NVIC_ClearPendingIRQ(i);
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break;
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}
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}
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}
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zassert_true(i >= 0, "No available IRQ line\n");
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return i;
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}
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static inline void trigger_irq(int irq)
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{
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printk("Triggering irq : %d\n", irq);
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#if defined(CONFIG_SOC_TI_LM3S6965_QEMU) || defined(CONFIG_CPU_CORTEX_M0) \
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|| defined(CONFIG_CPU_CORTEX_M0PLUS)
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NVIC_SetPendingIRQ(irq);
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#else
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NVIC->STIR = irq;
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#endif
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}
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#elif defined(CONFIG_GIC)
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#include <drivers/interrupt_controller/gic.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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static inline void trigger_irq(int irq)
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{
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printk("Triggering irq : %d\n", irq);
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/* Ensure that the specified IRQ number is a valid SGI interrupt ID */
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zassert_true(irq <= 15, "%u is not a valid SGI interrupt ID", irq);
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/*
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* Generate a software generated interrupt and forward it to the
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* requesting CPU.
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*/
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#if CONFIG_GIC_VER <= 2
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sys_write32(GICD_SGIR_TGTFILT_REQONLY | GICD_SGIR_SGIINTID(irq),
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GICD_SGIR);
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#else
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gic_raise_sgi(irq, GET_MPIDR(), BIT(MPIDR_TO_CORE(GET_MPIDR())));
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#endif
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}
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#elif defined(CONFIG_CPU_ARCV2)
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static inline void trigger_irq(int irq)
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{
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printk("Triggering irq : %d\n", irq);
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z_arc_v2_aux_reg_write(_ARC_V2_AUX_IRQ_HINT, irq);
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}
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#else
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/* for not supported architecture */
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#define NO_TRIGGER_FROM_SW
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#endif
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#endif /* INTERRUPT_UTIL_H_ */
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