Andrzej Głąbek 6bce789829 dts: Add and extend Nordic bindings needed for nRF54H20 ... Add a set of bindings that will be used in the nRF54H20 SoC definition. Extend the existing GPIOTE binding with properties needed for this SoC. Also do a tiny clean-up in the bindings added recently for nRF54L15 (HFXO and LFXO). Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no> Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com> Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>		2024-02-02 16:40:11 +01:00
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altr,nios2f.yaml
andes,andescore-v5.yaml	dts/riscv/andes: add andestech,andescore-v5 compatible string	2024-01-31 10:41:49 +01:00
arm,cortex-a53.yaml
arm,cortex-a55.yaml
arm,cortex-a72.yaml
arm,cortex-a76.yaml
arm,cortex-m0.yaml
arm,cortex-m0+.yaml
arm,cortex-m1.yaml
arm,cortex-m3.yaml
arm,cortex-m4.yaml
arm,cortex-m4f.yaml
arm,cortex-m7.yaml
arm,cortex-m23.yaml
arm,cortex-m33.yaml
arm,cortex-m33f.yaml
arm,cortex-m.yaml
arm,cortex-r4.yaml
arm,cortex-r4f.yaml
arm,cortex-r5.yaml
arm,cortex-r5f.yaml
arm,cortex-r7.yaml
arm,cortex-r52.yaml
arm,cortex-r82.yaml
cdns,tensilica-xtensa-lx3.yaml
cdns,tensilica-xtensa-lx4.yaml
cdns,tensilica-xtensa-lx6.yaml
cdns,tensilica-xtensa-lx7.yaml
cpu.yaml
efinix,vexriscv-sapphire.yaml	dts/riscv/efinix: add the efinix,vexriscv-sapphire compatible string	2024-01-31 10:41:49 +01:00
espressif,riscv.yaml
gaisler,leon3.yaml
intel,alder-lake.yaml
intel,apollo-lake.yaml
intel,elkhart-lake.yaml
intel,ish.yaml
intel,lakemont.yaml
intel,niosv.yaml
intel,raptor-lake.yaml
intel,x86.yaml
ite,riscv-ite.yaml
litex,vexriscv-standard.yaml	dts/riscv/litex: add litex,vexriscv-standard compatible string	2024-01-31 10:41:49 +01:00
lowrisc,ibex.yaml	dts/riscv/lowrisc: add lowrisc,ibex compatible string	2024-01-31 10:41:49 +01:00
neorv32-cpu.yaml
nordic,vpr.yaml	dts: Add and extend Nordic bindings needed for nRF54H20	2024-02-02 16:40:11 +01:00
nuclei,bumblebee.yaml	soc: riscv: gd32vf103: simplify MCAUSE exception mask handling	2024-01-15 09:58:03 +01:00
openisa,ri5cy.yaml	dts/riscv/openisa: add compatible strings for the RI5CY cores	2024-01-31 10:41:49 +01:00
openisa,zero-ri5cy.yaml	dts/riscv/openisa: add compatible strings for the RI5CY cores	2024-01-31 10:41:49 +01:00
qemu,nios2-zephyr.yaml
riscv,cpus.yaml	dts/bindings: move RISC-V cores bindings to dts/bindings/cpu/	2024-01-31 10:41:49 +01:00
sample_controller.yaml
sifive-common.yaml	dts/bindings: move RISC-V cores bindings to dts/bindings/cpu/	2024-01-31 10:41:49 +01:00
sifive,e24.yaml	dts/bindings: move RISC-V cores bindings to dts/bindings/cpu/	2024-01-31 10:41:49 +01:00
sifive,e31.yaml	dts/bindings: move RISC-V cores bindings to dts/bindings/cpu/	2024-01-31 10:41:49 +01:00
sifive,e51.yaml	dts/bindings: move RISC-V cores bindings to dts/bindings/cpu/	2024-01-31 10:41:49 +01:00
sifive,s7.yaml	dts/bindings: move RISC-V cores bindings to dts/bindings/cpu/	2024-01-31 10:41:49 +01:00
sifive,u54.yaml	dts/riscv/microchip: add missing cpu nodes compats in mpfs.dtsi	2024-01-31 10:41:49 +01:00
snps,arcem.yaml
telink,b91.yaml
zephyr,native-posix-cpu.yaml