99dcbdf933
This driver is impossible to make time-accurate using single-shot mode. Time accuracy may be obtained only by using periodic mode, meaning it is not tickless capable either. Let's simplify the code by only supporting periodic mode and strip out the TSC stuff. Any hardware with TSC capability should now use the apic-tsc driver instead. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
103 lines
3.1 KiB
Plaintext
103 lines
3.1 KiB
Plaintext
# Copyright (c) 2014-2015 Wind River Systems, Inc.
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# Copyright (c) 2016 Cadence Design Systems, Inc.
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# Copyright (c) 2019-2023 Intel Corp.
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# SPDX-License-Identifier: Apache-2.0
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choice
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prompt "Default System Timer"
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default HPET_TIMER if SOC_FAMILY_INTEL_ISH || SOC_ATOM || SOC_LAKEMONT
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default APIC_TSC_DEADLINE_TIMER
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depends on X86
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help
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Select Default System Timer.
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config HPET_TIMER
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bool "HPET timer"
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depends on DT_HAS_INTEL_HPET_ENABLED
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select IOAPIC
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select LOAPIC
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imply TIMER_READS_ITS_FREQUENCY_AT_RUNTIME
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select TICKLESS_CAPABLE
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select TIMER_HAS_64BIT_CYCLE_COUNTER
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help
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This option selects High Precision Event Timer (HPET) as a
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system timer.
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config APIC_TIMER
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bool "Local APIC timer"
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select LOAPIC
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select TIMER_HAS_64BIT_CYCLE_COUNTER
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select SYSTEM_CLOCK_LOCK_FREE_COUNT
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help
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Use the x86 local APIC in periodic mode as the system time
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source. NOTE: this probably isn't what you want except on
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older or idiosyncratic hardware (or environments like qemu
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without complete APIC emulation). Modern hardware will work
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better with CONFIG_APIC_TSC_DEADLINE_TIMER.
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config APIC_TSC_DEADLINE_TIMER
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bool "Local APIC timer using TSC deadline mode"
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select LOAPIC
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select TICKLESS_CAPABLE
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select TIMER_HAS_64BIT_CYCLE_COUNTER
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help
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Extremely simple timer driver based the local APIC TSC
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deadline capability. The use of a free-running 64 bit
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counter with comparator eliminates almost all edge cases
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from the handling, and the near-instruction-cycle resolution
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permits effectively unlimited precision where needed (the
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limit becomes the CPU time taken to execute the timing
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logic). SMP-safe and very fast, this should be the obvious
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choice for any x86 device with invariant TSC and TSC
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deadline capability.
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config APIC_TIMER_TSC
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bool "Local APIC timer using TSC time source"
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depends on !SMP
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select LOAPIC
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select TICKLESS_CAPABLE
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select TIMER_HAS_64BIT_CYCLE_COUNTER
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help
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If your CPU supports invariant TSC but no TSC deadline capability
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then this choice will rely on the TSC as time source and the
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local APIC in one-shot mode as the timeout event source.
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You must know the ratio of the TSC frequency to the local APIC
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timer frequency.
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endchoice
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if APIC_TIMER
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config APIC_TIMER_IRQ
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int "Local APIC timer IRQ"
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default 24
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help
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This option specifies the IRQ used by the local APIC timer.
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Note: this MUST be set to the index immediately after the
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last IO-APIC IRQ (the timer is the first entry in the APIC
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local vector table). This footgun is not intended to be
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user-configurable and almost certainly should be managed via
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a different mechanism.
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endif # APIC_TIMER
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if APIC_TIMER_TSC
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config APIC_TIMER_TSC_N
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int "TSC to local APIC timer frequency multiplier (N)"
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default 1
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config APIC_TIMER_TSC_M
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int "TSC to local APIC timer frequency divisor (M)"
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default 1
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endif # APIC_TIMER_TSC
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config APIC_TIMER_IRQ_PRIORITY
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int "Local APIC timer interrupt priority"
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depends on APIC_TIMER || APIC_TSC_DEADLINE_TIMER || APIC_TIMER_TSC
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default 4
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help
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This option specifies the interrupt priority used by the
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local APIC timer.
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