e6dfae0fea
The linker will emit a warning condition when a section with a declared alignment doesn't naturally start on that alignment (which begets the question of why the declared alignment syntax exists at all...). Do the alignment for .bss between the sections instead as a simple workaround. Note that this alignment isn't architecturally required, as current Zephyr targets don't use the page-aligned pseudo-MMU on this hardware; the only requirement is alignment to the 64 byte cache stride. It should work to pack .bss tightly. But when I try that, I get an error from the rimage tool, which is apparently unprepared for non-4k-aligned sections? Signed-off-by: Andy Ross <andrew.j.ross@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com> |
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| .. | ||
| esp32 | ||
| intel_adsp | ||
| intel_apl_adsp | ||
| intel_s1000 | ||
| sample_controller | ||
| CMakeLists.txt | ||