Andy Ross 0e83961b21 arch/xtensa: soc/xtensa/intel_adsp: Enable KERNEL_COHERENCE ... Implement the kernel "coherence" API on top of the linker cached/uncached mapping work. Add Xtensa handling for the stack coherence API. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>		2020-10-21 06:38:53 -04:00
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offsets
startup	Revert "arch: xtensa: Use reset-vector.S in booloader code"	2020-02-08 10:01:24 +02:00
atomic.S	kernel: add APIs for atomic os on pointers	2020-03-10 10:18:16 -04:00
CMakeLists.txt	arch: xtensa: Add support for Intel Apollolake	2020-02-05 10:43:25 -05:00
cpu_idle.c	tracing: move headers under include/tracing	2020-02-07 15:58:05 -05:00
crt1.S	arch/xtensa: Don't clear BSS on MP startup when !SMP	2020-10-21 06:38:53 -04:00
fatal.c	xtensa: add support to build HAL as part of build process	2019-12-18 20:24:18 -05:00
irq_manage.c	arch: Apply dynamic IRQ API change	2020-09-02 13:48:13 +02:00
irq_offload.c	isr: Normalize usage of device instance through ISR	2020-09-02 13:48:13 +02:00
window_vectors.S
xtensa_intgen.py
xtensa_intgen.tmpl
xtensa-asm2-util.S	arch/xtensa: soc/xtensa/intel_adsp: Enable KERNEL_COHERENCE	2020-10-21 06:38:53 -04:00
xtensa-asm2.c	arch/xtensa: soc/xtensa/intel_adsp: Enable KERNEL_COHERENCE	2020-10-21 06:38:53 -04:00