Jose Alberto Meza e2b34b96e3 soc: microchip: mec172x: Add CPU barriers during low power entry/exit ... Follow ARM architecture recommendations: * Use Data Synchronization Barrier (DSB) instruction before WFI, to ensure that pending memory transactions complete before changing state. * To guarantee pend interrupts are recognized before subsequent operation, use ISB after CPSIE (__irq_enable) This prevents sporadicy delayed ISRs due to continous MEC172x entering/exiting deep sleep. Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>		2024-08-27 18:37:11 -04:00
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common	soc: microchip: mec: Common SoC init updated to MEC5 HAL v0.2	2024-06-11 20:04:46 +03:00
mec15xx
mec172x	soc: microchip: mec172x: Add CPU barriers during low power entry/exit	2024-08-27 18:37:11 -04:00
mec174x	soc: microchip: mec: Add new HAL based MEC5 family chips	2024-05-21 16:45:30 -04:00
mec175x	soc: microchip: mec: Add new HAL based MEC5 family chips	2024-05-21 16:45:30 -04:00
mech172x	soc: microchip: mec: Add new HAL based MEC5 family chips	2024-05-21 16:45:30 -04:00
CMakeLists.txt
Kconfig	soc: microchip: mec: Add new HAL based MEC5 family chips	2024-05-21 16:45:30 -04:00
Kconfig.defconfig
Kconfig.soc
soc.yml	soc: microchip: mec: Add new HAL based MEC5 family chips	2024-05-21 16:45:30 -04:00