bb41d56ced
For ARM, Z_ARCH_EXCEPT triggers an SVC to induce a system error. This code block may be inlined, so, if we want to return from this error DIRECTLY to thread mode, e.g. if the system error occurred in ISR context and we are not aborting the current thread, we must instruct the compiler that the execution may continue after the inlined SVC. Therefore, we must remove the CODE_UNREACHABLE statements. Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
66 lines
1.7 KiB
C
66 lines
1.7 KiB
C
/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Cortex-M public error handling
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*
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* ARM-specific kernel error handling interface. Included by arm/arch.h.
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_M_ERROR_H_
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#define ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_M_ERROR_H_
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#include <arch/arm/syscall.h>
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#include <arch/arm/exc.h>
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#include <stdbool.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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/* ARMv6 will hard-fault if SVC is called with interrupts locked. Just
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* force them unlocked, the thread is in an undefined state anyway
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*
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* On ARMv7m we won't get a HardFault, but if interrupts were locked the
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* thread will continue executing after the exception and forbid PendSV to
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* schedule a new thread until they are unlocked which is not what we want.
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* Force them unlocked as well.
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*/
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#define Z_ARCH_EXCEPT(reason_p) \
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register u32_t r0 __asm__("r0") = reason_p; \
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do { \
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__asm__ volatile ( \
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"cpsie i\n\t" \
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"svc %[id]\n\t" \
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: \
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: "r" (r0), [id] "i" (_SVC_CALL_RUNTIME_EXCEPT) \
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: "memory"); \
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} while (false)
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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#define Z_ARCH_EXCEPT(reason_p) do { \
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__asm__ volatile ( \
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"eors.n r0, r0\n\t" \
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"msr BASEPRI, r0\n\t" \
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"mov r0, %[reason]\n\t" \
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"svc %[id]\n\t" \
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: \
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: [reason] "i" (reason_p), [id] "i" (_SVC_CALL_RUNTIME_EXCEPT) \
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: "memory"); \
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} while (false)
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#elif defined(CONFIG_ARMV7_R)
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/* Pick up the default definition in kernel.h for now */
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_M_ERROR_H_ */
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