Sylvio Alves e48fe49a70 soc: esp32s3: appcpu: add sram dts information ... Make sure SoC has defined RAM size. Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>		2024-03-20 07:55:09 -05:00
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espressif	soc: esp32s3: appcpu: add sram dts information	2024-03-20 07:55:09 -05:00
intel	dts: xtensa: intel_adsp: Remove ALH nodes from ACE 2.0 LNL DTS	2024-03-19 14:54:29 +01:00
nxp	dts: xtensa: nxp_imx8: add EDMA0 node	2024-03-13 22:37:04 +00:00
dc233c.dtsi	xtensa: dc233c: enlarge ROM space	2023-09-14 17:07:21 -04:00
sample_controller.dtsi
xtensa.dtsi