zephyr/soc
Rajavardhan Gundi 4df8ba3fe0 linker: intel_s1000: Remove limits on code and data sections
All text, data and bss sections are all mapped to the same physical
memory (SRAM). This patch removes the individual section limits
and defines a common limit for the sum of text, data and bss sections.
This would make it more flexible for application developers.

Fixes #11268.

Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
2018-12-10 22:05:06 -05:00
..
arc soc: arc: clean up the timer relatted definitions 2018-12-07 17:08:15 -05:00
arm arm: silabs: Enable DCDC before setting up clk 2018-12-07 13:55:31 -06:00
nios2 Kconfig: Use 'default' instead of 'def_bool' in Kconfig.defconfig files 2018-11-13 16:04:01 -05:00
posix kernel: Remove _IntLibInit function 2018-11-28 14:59:10 -08:00
riscv32 arch: riscv32: provide a general mechanism for saving SoC context 2018-12-04 22:54:23 -05:00
x86 soc: Add 'U' to unsigned variable assignments 2018-12-04 22:51:56 -05:00
xtensa linker: intel_s1000: Remove limits on code and data sections 2018-12-10 22:05:06 -05:00
Kconfig linker: allow SoC to insert linker script fragments 2018-10-19 16:11:34 -04:00