zephyr/dts/riscv
Marcio Ribeiro 674529e11b dts: esp32: fix sram0 start address for esp32c2 and esp32c3
Changes the sram0 start address from 0x4037_0000 to 0x4037_C000 for:
- esp32c2
- esp32c3

Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
2024-12-12 19:59:44 +01:00
..
andes dts/andes: adjust the sizes of PLIC nodes 2024-10-31 14:17:02 -05:00
efinix dts: riscv: Fix incorrect plic size 2024-07-02 22:21:17 -04:00
espressif dts: esp32: fix sram0 start address for esp32c2 and esp32c3 2024-12-12 19:59:44 +01:00
gd
ite drivers: mfd: it8801_altctrl: Add alternate controller for MFD 2024-12-03 19:56:50 +01:00
lowrisc
microchip
niosv
nordic soc: nordic: Introduce the nRF54L05 and nRF54L10 2024-11-21 09:26:38 +01:00
openisa soc/openisa: enable the C extension 2024-07-03 15:06:14 -04:00
qemu arch: riscv64: smp: get msip base address from dts 2024-11-27 06:58:57 -05:00
sensry board: sensry: Add support for sy1xx 2024-09-16 20:19:31 +02:00
sifive boards: hifive_unmatched: add support for S7 and U74 targets 2024-11-20 10:15:03 +00:00
starfive
telink
wch drivers: add the ch32v00x clock controller 2024-11-26 14:41:46 +00:00
neorv32.dtsi
renode_riscv32_virt.dtsi
riscv32-litex-vexriscv.dtsi drivers: watchdog: litex: add litex watchdog 2024-08-19 10:02:01 -04:00