Pierre-Emmanuel Novac 0e510cc2a6 drivers/clock_control: stm32: Configure and enable PLL2 ... DT node "st,stm32f105-pll2-clock" already exists but was not actually used and PLL2 was not being configured. PLL2 is available on STM32F105/F107 and should be turned off after turning off PLL and turned on before turning on PLL again since PLL2 can be used as a source for PLL. Source for PLL2 is always HSE. Signed-off-by: Pierre-Emmanuel Novac <piernov@piernov.org>		2022-09-09 16:28:15 -04:00
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mgmt/mcumgr	mgmt: mcumgr: Add dummy SMP backend	2022-09-08 15:29:21 +00:00
zephyr	drivers/clock_control: stm32: Configure and enable PLL2	2022-09-09 16:28:15 -04:00