Andrew Boie 506f15c381 interrupts: simplify position of sw ISR table ... We now place the linker directives for the SW ISR table in the common linker scripts, instead of repeating it everywhere. The table will be placed in RAM if dynamic interrupts are enabled. A dedicated section is used, as this data must not move in between build phases. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>		2018-11-10 11:01:22 -05:00
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arc	kconfig: Hide the DesignWare I2C driver on unsupported platforms	2018-10-25 07:32:05 +01:00
arm	gpio: stm32 use dts extracted information to populate gpio instances.	2018-11-09 04:49:59 -06:00
nios2	DT: Rename from dts.fixup to dts_fixup.h	2018-10-08 11:38:56 -04:00
posix	posix arch: Improve description of posix_halt_cpu	2018-10-27 21:35:51 -04:00
riscv32	qemu_riscv32: use hifive1 configuration	2018-11-05 11:00:38 -05:00
x86	soc: Remove useless Kconfig options and config for Galileo and SPI	2018-11-09 05:25:11 -06:00
xtensa	interrupts: simplify position of sw ISR table	2018-11-10 11:01:22 -05:00
Kconfig	linker: allow SoC to insert linker script fragments	2018-10-19 16:11:34 -04:00