Marcin Szkudlinski c01a8c8807 mtl: soc: store power gating state in D3 state ... Power gating register must be stored when CPU is in power off state Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>		2022-11-18 13:00:04 -05:00
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arc	boards: nsim_hs: Add separate config for XIP memory organization	2022-11-16 11:18:51 +01:00
arm	soc: Updated clock_init in rt6xx	2022-11-17 13:59:39 -06:00
arm64	boards/arm64: Add QEMU Virt KVM support	2022-11-17 11:16:08 +01:00
mips
nios2
posix	cmake: Update CONFIG_ASAN support	2022-08-19 08:30:01 +02:00
riscv	ITE: soc: chip_chipregs: Add SPISC register structure	2022-11-09 10:44:29 +01:00
sparc
x86	soc: x86: Used fixed BDF values for early serial	2022-11-16 11:18:43 +01:00
xtensa	mtl: soc: store power gating state in D3 state	2022-11-18 13:00:04 -05:00
Kconfig	soc: Add ability for SOC to specify runtime CPU detection	2022-11-03 16:43:53 -04:00