d79d4f0bea
GD32V SoC uses divided clock from core-clock for machine timer clock. Add config of clock divide factor to support GD32V. Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
23 lines
877 B
C
23 lines
877 B
C
/*
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* Copyright (c) 2021, TOKITA Hiroshi <tokita.hiroshi@gmail.com>
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_TIMER_RISCV_MACHINE_TIMER_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_TIMER_RISCV_MACHINE_TIMER_H_
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/* Clock divider values */
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#define RISCV_MACHINE_TIMER_DIVIDER_1 0
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#define RISCV_MACHINE_TIMER_DIVIDER_2 1
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#define RISCV_MACHINE_TIMER_DIVIDER_4 2
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#define RISCV_MACHINE_TIMER_DIVIDER_8 3
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#define RISCV_MACHINE_TIMER_DIVIDER_16 4
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#define RISCV_MACHINE_TIMER_DIVIDER_32 5
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#define RISCV_MACHINE_TIMER_DIVIDER_64 6
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#define RISCV_MACHINE_TIMER_DIVIDER_128 7
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#define RISCV_MACHINE_TIMER_DIVIDER_256 8
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#define RISCV_MACHINE_TIMER_DIVIDER_512 9
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#define RISCV_MACHINE_TIMER_DIVIDER_1024 10
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#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_TIMER_RISCV_MACHINE_TIMER_H_ */
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