d3f6b54f8e
Implement a clock control driver for Microchip MEC172x handling configuring the 32 KHz input sources for the PLL and peripheral-32k clock domains. MEC172x differs from MEC152x. MEC152x had one 32K source for both PLL and peripherals. MEC172x allows the two domains to use independent 32 KHz sources. Device tree updated to provide addresses of hardware used by the driver. Signed-off-by: Scott Worley <scott.worley@microchip.com>
25 lines
715 B
C
25 lines
715 B
C
/*
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* Copyright (c) 2021 Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_MCHP_XEC_H_
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#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_MCHP_XEC_H_
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#include <drivers/clock_control.h>
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#include <dt-bindings/clock/mchp_xec_pcr.h>
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/*
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* Set/clear Microchip XEC peripheral sleep enable.
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* SoC layer contains the chip specific sleep index and positions
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*/
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int z_mchp_xec_pcr_periph_sleep(uint8_t slp_idx, uint8_t slp_pos,
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uint8_t slp_en);
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#if defined(CONFIG_PM)
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void mchp_xec_clk_ctrl_sys_sleep_enable(bool is_deep);
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void mchp_xec_clk_ctrl_sys_sleep_disable(void);
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#endif
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#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_LPC11U6X_CLOCK_CONTROL_H_ */
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