0369998e61
MIPS (Microprocessor without Interlocked Pipelined Stages) is a instruction set architecture (ISA) developed by MIPS Computer Systems, now MIPS Technologies. This commit provides MIPS architecture support to Zephyr. It is compatible with the MIPS32 Release 1 specification. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
55 lines
1.2 KiB
C
55 lines
1.2 KiB
C
/*
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* Copyright (c) 2020 Antony Pavlov <antonynpavlov@gmail.com>
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*
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* based on include/arch/riscv/thread.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Per-arch thread definition
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*
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* This file contains definitions for
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*
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* struct _thread_arch
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* struct _callee_saved
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*
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* necessary to instantiate instances of struct k_thread.
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_MIPS_THREAD_H_
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#define ZEPHYR_INCLUDE_ARCH_MIPS_THREAD_H_
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#ifndef _ASMLANGUAGE
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#include <zephyr/types.h>
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/*
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* The following structure defines the list of registers that need to be
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* saved/restored when a cooperative context switch occurs.
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*/
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struct _callee_saved {
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ulong_t sp; /* Stack pointer */
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ulong_t s0; /* saved register */
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ulong_t s1; /* saved register */
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ulong_t s2; /* saved register */
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ulong_t s3; /* saved register */
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ulong_t s4; /* saved register */
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ulong_t s5; /* saved register */
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ulong_t s6; /* saved register */
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ulong_t s7; /* saved register */
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ulong_t s8; /* saved register AKA fp */
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};
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typedef struct _callee_saved _callee_saved_t;
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struct _thread_arch {
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uint32_t swap_return_value; /* Return value of z_swap() */
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};
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typedef struct _thread_arch _thread_arch_t;
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#endif /* _ASMLANGUAGE */
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#endif /* ZEPHYR_INCLUDE_ARCH_MIPS_THREAD_H_ */
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