0369998e61
MIPS (Microprocessor without Interlocked Pipelined Stages) is a instruction set architecture (ISA) developed by MIPS Computer Systems, now MIPS Technologies. This commit provides MIPS architecture support to Zephyr. It is compatible with the MIPS32 Release 1 specification. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
62 lines
1.4 KiB
C
62 lines
1.4 KiB
C
/*
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* Copyright (c) 2021 Antony Pavlov <antonynpavlov@gmail.com>
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*
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* based on include/arch/riscv/exp.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_MIPS_EXP_H_
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#define ZEPHYR_INCLUDE_ARCH_MIPS_EXP_H_
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#ifndef _ASMLANGUAGE
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#include <zephyr/types.h>
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#include <toolchain.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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struct __esf {
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ulong_t ra; /* return address */
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ulong_t gp; /* global pointer */
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ulong_t t0; /* Caller-saved temporary register */
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ulong_t t1; /* Caller-saved temporary register */
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ulong_t t2; /* Caller-saved temporary register */
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ulong_t t3; /* Caller-saved temporary register */
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ulong_t t4; /* Caller-saved temporary register */
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ulong_t t5; /* Caller-saved temporary register */
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ulong_t t6; /* Caller-saved temporary register */
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ulong_t t7; /* Caller-saved temporary register */
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ulong_t t8; /* Caller-saved temporary register */
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ulong_t t9; /* Caller-saved temporary register */
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ulong_t a0; /* function argument */
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ulong_t a1; /* function argument */
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ulong_t a2; /* function argument */
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ulong_t a3; /* function argument */
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ulong_t v0; /* return value */
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ulong_t v1; /* return value */
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ulong_t at; /* assembly temporary */
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ulong_t epc;
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ulong_t badvaddr;
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ulong_t hi;
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ulong_t lo;
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ulong_t status;
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ulong_t cause;
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};
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typedef struct __esf z_arch_esf_t;
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ASMLANGUAGE */
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#endif /* ZEPHYR_INCLUDE_ARCH_MIPS_EXP_H_ */
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