0369998e61
MIPS (Microprocessor without Interlocked Pipelined Stages) is a instruction set architecture (ISA) developed by MIPS Computer Systems, now MIPS Technologies. This commit provides MIPS architecture support to Zephyr. It is compatible with the MIPS32 Release 1 specification. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
118 lines
2.3 KiB
C
118 lines
2.3 KiB
C
/*
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* Copyright (c) 2020 Antony Pavlov <antonynpavlov@gmail.com>
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*
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* based on include/arch/sparc/arch.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_MIPS_ARCH_H_
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#define ZEPHYR_INCLUDE_ARCH_MIPS_ARCH_H_
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#include <arch/mips/thread.h>
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#include <arch/mips/exp.h>
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#include <arch/common/sys_bitops.h>
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#include <arch/common/sys_io.h>
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#include <arch/common/ffs.h>
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#include <irq.h>
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#include <sw_isr_table.h>
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#include <devicetree.h>
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#include <mips/mipsregs.h>
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#define ARCH_STACK_PTR_ALIGN 16
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#define OP_LOADREG lw
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#define OP_STOREREG sw
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#define CP0_STATUS_DEF_RESTORE (ST0_EXL | ST0_IE)
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#ifndef _ASMLANGUAGE
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#include <sys/util.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define STACK_ROUND_UP(x) ROUND_UP(x, ARCH_STACK_PTR_ALIGN)
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void arch_irq_enable(unsigned int irq);
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void arch_irq_disable(unsigned int irq);
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int arch_irq_is_enabled(unsigned int irq);
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void z_irq_spurious(const void *unused);
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/**
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* Configure a static interrupt.
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*
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* All arguments must be computable by the compiler at build time.
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*
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* @param irq_p IRQ line number
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* @param priority_p Interrupt priority
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* @param isr_p Interrupt service routine
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* @param isr_param_p ISR parameter
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* @param flags_p IRQ options
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*
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* @return The vector assigned to this interrupt
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*/
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#define ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
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{ \
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Z_ISR_DECLARE(irq_p, 0, isr_p, isr_param_p); \
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}
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static ALWAYS_INLINE unsigned int arch_irq_lock(void)
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{
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uint32_t status = read_c0_status();
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if (status & ST0_IE) {
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write_c0_status(status & ~ST0_IE);
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return 1;
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}
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return 0;
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}
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static ALWAYS_INLINE void arch_irq_unlock(unsigned int key)
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{
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uint32_t status = read_c0_status();
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if (key) {
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status |= ST0_IE;
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} else {
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status &= ~ST0_IE;
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}
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write_c0_status(status);
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}
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static ALWAYS_INLINE bool arch_irq_unlocked(unsigned int key)
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{
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return key != 0;
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}
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static ALWAYS_INLINE void arch_nop(void)
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{
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__asm__ volatile ("nop");
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}
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extern uint32_t sys_clock_cycle_get_32(void);
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static inline uint32_t arch_k_cycle_get_32(void)
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{
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return sys_clock_cycle_get_32();
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}
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extern uint64_t sys_clock_cycle_get_64(void);
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static inline uint64_t arch_k_cycle_get_64(void)
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{
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return sys_clock_cycle_get_64();
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ASMLANGUAGE */
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#endif /* ZEPHYR_INCLUDE_ARCH_MIPS_ARCH_H_ */
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