38d684f8f1
Exposes the RC register so that the initial value can be set in the device tree. This is useful in the case where the timer generates an event but an interrupt is not required. e.g generate event to sample adc on RC register match. Tested on Atmel SMART SAM E70 Xplained Ultra board Signed-off-by: Marius Scholtz <mariuss@ricelectronics.com> |
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| .. | ||
| arm,armv8-timer.yaml | ||
| arm,cmsdk-dtimer.yaml | ||
| arm,cmsdk-timer.yaml | ||
| atmel,sam0-tc32.yaml | ||
| atmel,sam-tc.yaml | ||
| espressif,esp32-systimer.yaml | ||
| gaisler,gptimer.yaml | ||
| gd,gd32-timer.yaml | ||
| intel,hpet.yaml | ||
| ite,it8xxx2-timer.yaml | ||
| litex,timer0.yaml | ||
| microchip,xec-rtos-timer.yaml | ||
| nordic,nrf-timer.yaml | ||
| nuvoton,npcx-itim-timer.yaml | ||
| nxp,imx-gpt.yaml | ||
| nxp,lpc-ctimer.yaml | ||
| openisa,rv32m1-lptmr.yaml | ||
| renesas,rcar-cmt.yaml | ||
| riscv,machine-timer.yaml | ||
| silabs,gecko-timer.yaml | ||
| st,stm32-lptim.yaml | ||
| st,stm32-timers.yaml | ||
| xlnx,ttcps.yaml | ||