5599f1b3ab
This change provides support for 4 IO read (via 4READ command) and program (via 4PP). Flash memory pins SIO[0123], CLK and CS are used. All of them are controlled by stm32 QSPI IP block. The instruction code for fast reading as well as number of latency cycles required are read from SFDP structure provided by flash memory. The number of required read latency cycles when performing reading is the sum of SPI-NOR memory mode bits and wait states (also named as 'dummy cycles'). It also has been assumed that memory, which supports fast read (4READ), also will support fast programming (4PP command) as this information is not available in SFDP. One also need to enable the QUAD IO support in board's device tree by defining 'spi-bus-width = <4>' property. It is required as it may happen that not all QSPI dedicated pins are used (for example only two of them are available). Signed-off-by: Lukasz Majewski <lukma@denx.de>
54 lines
2.2 KiB
C
54 lines
2.2 KiB
C
/*
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* Copyright (c) 2018 Savoir-Faire Linux.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __SPI_NOR_H__
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#define __SPI_NOR_H__
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#include <sys/util.h>
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#define SPI_NOR_MAX_ID_LEN 3
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/* Status register bits */
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#define SPI_NOR_WIP_BIT BIT(0) /* Write in progress */
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#define SPI_NOR_WEL_BIT BIT(1) /* Write enable latch */
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#define SPI_NOR_QE_BIT BIT(6) /* Enable quad mode */
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/* Control register bits */
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#define SPI_NOR_4BYTE_BIT BIT(5) /* 4B addressing */
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/* Flash opcodes */
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#define SPI_NOR_CMD_WRSR 0x01 /* Write status register */
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#define SPI_NOR_CMD_RDSR 0x05 /* Read status register */
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#define SPI_NOR_CMD_READ 0x03 /* Read data */
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#define SPI_NOR_CMD_DREAD 0x3B /* Read data (1-1-2) */
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#define SPI_NOR_CMD_QREAD 0x6B /* Read data (1-1-4) */
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#define SPI_NOR_CMD_4READ 0xEB /* Read data (1-4-4) */
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#define SPI_NOR_CMD_WREN 0x06 /* Write enable */
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#define SPI_NOR_CMD_WRDI 0x04 /* Write disable */
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#define SPI_NOR_CMD_PP 0x02 /* Page program */
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#define SPI_NOR_CMD_4PP 0x38 /* Page program (1-4-4) */
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#define SPI_NOR_CMD_RDCR 0x15 /* Read control register */
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#define SPI_NOR_CMD_SE 0x20 /* Sector erase */
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#define SPI_NOR_CMD_BE_32K 0x52 /* Block erase 32KB */
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#define SPI_NOR_CMD_BE 0xD8 /* Block erase */
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#define SPI_NOR_CMD_CE 0xC7 /* Chip erase */
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#define SPI_NOR_CMD_RDID 0x9F /* Read JEDEC ID */
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#define SPI_NOR_CMD_ULBPR 0x98 /* Global Block Protection Unlock */
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#define SPI_NOR_CMD_4BA 0xB7 /* Enter 4-Byte Address Mode */
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#define SPI_NOR_CMD_DPD 0xB9 /* Deep Power Down */
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#define SPI_NOR_CMD_RDPD 0xAB /* Release from Deep Power Down */
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/* Page, sector, and block size are standard, not configurable. */
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#define SPI_NOR_PAGE_SIZE 0x0100U
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#define SPI_NOR_SECTOR_SIZE 0x1000U
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#define SPI_NOR_BLOCK_SIZE 0x10000U
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/* Test whether offset is aligned to a given number of bits. */
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#define SPI_NOR_IS_ALIGNED(_ofs, _bits) (((_ofs) & BIT_MASK(_bits)) == 0)
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#define SPI_NOR_IS_SECTOR_ALIGNED(_ofs) SPI_NOR_IS_ALIGNED(_ofs, 12)
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#endif /*__SPI_NOR_H__*/
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