1e9ada4eb9
Intel's adsp needs to set, at a minimum, a clocking bit before the driver can initialize the designware dma controller. In many ways it is the designware dmac IP but with additional registers and functionality added on top of it. So the code structure here follows how the hardware appears to be designed, layered on top of the designware driver. Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
50 lines
947 B
Plaintext
50 lines
947 B
Plaintext
# DMA configuration options
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# Copyright (c) 2016 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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#
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# DMA options
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#
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menuconfig DMA
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bool "DMA driver Configuration"
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if DMA
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config DMA_64BIT
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bool "DMA 64 bit address support"
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help
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When this option is true, 64 bit source and dest
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DMA addresses are supported.
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config DMA_INIT_PRIORITY
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int "DMA init priority"
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default KERNEL_INIT_PRIORITY_DEFAULT
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help
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DMA driver device initialization priority.
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module = DMA
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module-str = dma
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source "subsys/logging/Kconfig.template.log_config"
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source "drivers/dma/Kconfig.stm32"
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source "drivers/dma/Kconfig.sam_xdmac"
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source "drivers/dma/Kconfig.dw"
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source "drivers/dma/Kconfig.nios2_msgdma"
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source "drivers/dma/Kconfig.sam0"
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source "drivers/dma/Kconfig.mcux_edma"
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source "drivers/dma/Kconfig.mcux_lpc"
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source "drivers/dma/Kconfig.dma_pl330"
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source "drivers/dma/Kconfig.iproc_pax"
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source "drivers/dma/Kconfig.cavs_gpdma"
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endif # DMA
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