If frequency of the system clock is lower then deviation may exceed default value (10us). Instead of adjusting the default value, test is rounding up expected standard deviation to a single clock cycle. Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no> |
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| .. | ||
| jitter_drift.c | ||
| main.c | ||
| tick_timer_train.c | ||