c5b93effe1
The DPSRAM ports can run at different clocks, this is the default configuration, follow the advice in the datasheet and wait 3 nop instructions before setting the AVAILABLE bit. It can be observed that when the controller is continuously sending data to the host, it rarely has a 0-byte transaction instead of a short packet. The reason for this is not easy to find, it also seems to depend on the runtime of individual components. This may fix the problem, but there is no sure proof that this is the solution. Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no> |
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| .. | ||
| bc12 | ||
| common | ||
| device | ||
| udc | ||
| uhc | ||
| uvb | ||
| CMakeLists.txt | ||
| Kconfig | ||