c989f0b408
riscv defines the machine-mode timer registers that are implemented by the all riscv SOCs that follow the riscv privileged architecture specification. The timer registers implemented in riscv-qemu follow this specification. To account for future riscv SOCs, reimplement the riscv_qemu_driver by the riscv_machine_driver. Change-Id: I645b03c91b4e07d0f2609908decc27ba9b8240d4 Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
12 lines
417 B
Makefile
12 lines
417 B
Makefile
obj-$(CONFIG_HPET_TIMER) += hpet.o
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obj-$(CONFIG_LOAPIC_TIMER) += loapic_timer.o
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obj-$(CONFIG_ARCV2_TIMER) += arcv2_timer0.o
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obj-$(CONFIG_ALTERA_AVALON_TIMER) += altera_avalon_timer.o
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obj-$(CONFIG_NRF_RTC_TIMER) += nrf_rtc_timer.o
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obj-$(CONFIG_PULPINO_TIMER) += pulpino_timer.o
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obj-$(CONFIG_RISCV_MACHINE_TIMER) += riscv_machine_timer.o
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obj-$(CONFIG_CORTEX_M_SYSTICK) += cortex_m_systick.o
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obj-y += sys_clock_init.o
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