Daniel Leung e55fb88bcb soc: intel_adsp/ace: update clock rate ... The clock rates for ACE series of Intel Audio DSP have changed. The values come from the SOF project in their board configs. CONFIG_XTENSA_CCOUNT_HZ is also set so the arch timing test can pass. Signed-off-by: Daniel Leung <daniel.leung@intel.com>		2023-07-17 16:27:08 -04:00
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arc	ARC: Turn off stack checking for hsdk4xd	2023-07-10 09:29:43 +02:00
arm	soc: arm: lpc55xxx: Updated clock init	2023-07-17 13:05:44 -05:00
arm64	soc: arm64: add PFC files to Renesas r8a77961 Gen3 SoC	2023-07-11 11:17:41 +02:00
mips
nios2
posix	soc inf (native): Refactor into a top and bottom	2023-06-23 12:16:26 +02:00
riscv	soc: riscv: andes_v5: remove redundant CONFIG_CACHE_ENABLE	2023-07-17 10:10:31 +00:00
sparc
x86	boards: rpl_crb: Indicate support for SMBus	2023-04-04 08:15:00 -04:00
xtensa	soc: intel_adsp/ace: update clock rate	2023-07-17 16:27:08 -04:00
Kconfig	nrf52_bsim: Convert from a nRF52832 to a nRF52833	2023-01-26 09:29:18 +01:00