This patchset is doing three things: 1. It is fixing the bogus algorithm to find the optimal number of descriptors for a given memory size. 2. It is changing values for VDEV_STATUS_SIZE and IPC_SERVICE_STATIC_VRINGS_ALIGNMENT to better align to a usual cache line size. 3. RX/TX VRINGs are now correctly aligned to MEM_ALIGNMENT (and cache line alignment). Signed-off-by: Carlo Caione <ccaione@baylibre.com> |
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| arc/synopsys | ||
| arm | ||
| arm64 | ||
| bindings | ||
| common | ||
| nios2/intel | ||
| posix | ||
| riscv | ||
| sparc/gaisler | ||
| x86/intel | ||
| xtensa | ||
| binding-template.yaml | ||
| Kconfig | ||