Some STM32 series (l0, g0, f0) needs to enable clock of DBGMCU peripheral, before accessing registers Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com> |
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|---|---|---|
| .. | ||
| arc | ||
| arm | ||
| arm64 | ||
| nios2 | ||
| posix | ||
| riscv | ||
| sparc | ||
| x86 | ||
| xtensa | ||
| Kconfig | ||
Some STM32 series (l0, g0, f0) needs to enable clock of DBGMCU peripheral, before accessing registers Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com> |
||
|---|---|---|
| .. | ||
| arc | ||
| arm | ||
| arm64 | ||
| nios2 | ||
| posix | ||
| riscv | ||
| sparc | ||
| x86 | ||
| xtensa | ||
| Kconfig | ||