Nicolas Pitre 7f74825958 riscv: add a qemu_riscv64 board ... This emulates a RISC-V in 64-bit mode on a SiFive FE310 dev board. Memory is tight so a few tests had to be disabled due to the extra memory usage compared to qemu_riscv32. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>		2019-08-09 09:11:45 -05:00
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base64	tests: base64: add tests for error paths	2019-07-30 10:14:41 -07:00
c_lib	libc: minimal: add strspn and strcspn support	2019-07-31 09:22:49 -07:00
crc	tests: crc: convert to regular test case	2019-07-06 00:31:04 +02:00
fdtable	tests: fdtable: add tests	2019-07-22 16:36:15 -07:00
json	tests: json: improve code coverage	2019-07-02 22:56:53 -04:00
mem_alloc	tests: mem_alloc: don't set main thread size	2019-07-01 14:30:48 -07:00
rbtree	riscv: add a qemu_riscv64 board	2019-08-09 09:11:45 -05:00
ringbuffer	cleanup: include/: move ring_buffer.h to sys/ring_buffer.h	2019-06-27 22:55:49 -04:00
sprintf	prf.c: handle denormals properly	2019-07-14 23:07:44 -04:00
timeutil	libc/minimal: fix reproducibility of gmtime	2019-07-31 11:48:18 +03:00