1f4b5ddd0f
With the upcoming riscv64 support, it is best to use "riscv" as the subdirectory name and common symbols as riscv32 and riscv64 support code is almost identical. Then later decide whether 32-bit or 64-bit compilation is wanted. Redirects for the web documentation are also included. Then zephyrbot complained about this: " New files added that are not covered in CODEOWNERS: dts/riscv/microsemi-miv.dtsi dts/riscv/riscv32-fe310.dtsi Please add one or more entries in the CODEOWNERS file to cover those files " So I assigned them to those who created them. Feel free to readjust as necessary. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
47 lines
909 B
C
47 lines
909 B
C
/*
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* Copyright (c) 2018 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <ztest.h>
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#include <irq_offload.h>
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#include <kernel_structs.h>
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#if defined(CONFIG_ARM)
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#include <arch/arm/cortex_m/cmsis.h>
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static void trigger_irq(int irq)
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{
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printk("Triggering irq : %d\n", irq);
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#if defined(CONFIG_SOC_TI_LM3S6965_QEMU) || defined(CONFIG_CPU_CORTEX_M0) \
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|| defined(CONFIG_CPU_CORTEX_M0PLUS)
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NVIC_SetPendingIRQ(irq);
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#else
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NVIC->STIR = irq;
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#endif
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}
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#elif defined(CONFIG_RISCV)
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static void trigger_irq(int irq)
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{
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u32_t mip;
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printk("Triggering irq : %d\n", irq);
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__asm__ volatile ("csrrs %0, mip, %1\n"
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: "=r" (mip)
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: "r" (1 << irq));
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}
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#elif defined(CONFIG_CPU_ARCV2)
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static void trigger_irq(int irq)
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{
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printk("Triggering irq : %d\n", irq);
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z_arc_v2_aux_reg_write(_ARC_V2_AUX_IRQ_HINT, irq);
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}
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#else
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/* for not supported architecture */
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#define NO_TRIGGER_FROM_SW
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#endif
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