0343118abb
Currently we are using mxcsr register with the bit 6 DAZ enabled. When the denormals-are-zeros flag is set, the processor converts all denormal source operands to a zero with the sign of the original operand before performing any computations on them. It causes bugs in the SIMD XMM registers computation like #38646 I suggest to disable Denormals-Are-Zeros flag and mask division-by-zero exception. Set value to the default 1F80H according to the Intel(R) 64 and IA-32 Architectures Software Developer's Manual. Fix will let all x86 boards perform SIMD computation using XMM registers in the correct way. Fixes #38646 Signed-off-by: Maksim Masalski <maksim.masalski@intel.com> |
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| .. | ||
| arc | ||
| arm/aarch32 | ||
| arm64 | ||
| common | ||
| nios2 | ||
| posix | ||
| riscv | ||
| sparc | ||
| x86 | ||
| xtensa | ||
| arch_inlines.h | ||
| cpu.h | ||
| structs.h | ||
| syscall.h | ||