Evgeniy Paltsev 6ce3c531d8 ARC: ARcv3: 64bit: manage accumulator reg properly ... In case of ARCv3 64 bit we have only one 64bit accumulator register instead of register pair, so fixup register save & restore code. While we at it also make ARC_HAS_ACCL_REGS option (which controls accumulator reg/regs save & restore) default for HS5x and HS6x as well - as it should be. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>		2022-08-19 12:09:37 +02:00
..
mpu	arch: arc: remove unused <soc.h>	2022-08-03 07:46:14 -04:00
offsets	ARC: ARcv3: 64bit: manage accumulator reg properly	2022-08-19 12:09:37 +02:00
secureshield	arch: arc: remove unused <soc.h>	2022-08-03 07:46:14 -04:00
arc_connect.c
arc_smp.c	soc: arc: define ICI in DT	2022-08-03 07:46:14 -04:00
cache.c
CMakeLists.txt
cpu_idle.S	asm: update files with <zephyr/...> include prefix	2022-05-09 12:45:29 -04:00
fast_irq.S	ARC: fix SMP race in ASM ARC interrupt handling code	2022-07-20 09:26:24 -05:00
fatal.c
fault_s.S	ARC: fix SMP race in ASM ARC interrupt handling code	2022-07-20 09:26:24 -05:00
fault.c
irq_manage.c
irq_offload.c
isr_wrapper.S	ARC: ARcv3: 64bit: manage accumulator reg properly	2022-08-19 12:09:37 +02:00
prep_c.c
regular_irq.S	ARC: fix SMP race in ASM ARC interrupt handling code	2022-07-20 09:26:24 -05:00
reset.S	asm: update files with <zephyr/...> include prefix	2022-05-09 12:45:29 -04:00
switch.S	asm: update files with <zephyr/...> include prefix	2022-05-09 12:45:29 -04:00
thread_entry_wrapper.S	asm: update files with <zephyr/...> include prefix	2022-05-09 12:45:29 -04:00
thread.c	ARC: fix SMP race in ASM ARC interrupt handling code	2022-07-20 09:26:24 -05:00
timestamp.c
tls.c
userspace.S	asm: update files with <zephyr/...> include prefix	2022-05-09 12:45:29 -04:00
vector_table.c
vector_table.ld	arc: vector_table: Automatically place the IRQ vector table	2022-06-28 12:29:42 +02:00