ccad9d0d09
Move test related code and the testsuite away from tests/ and make it a proper subsystem. The way tests were integrate in the tree was not obvious and actual tests were intermixed with the testsuite code. This will allow us to have trees with the testcode and without the samples by just remove the folders tests/ and samples, needed for isolating actual code from test/sample code. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
54 lines
1.2 KiB
C
54 lines
1.2 KiB
C
/* GCC specific test inline assembler functions and macros */
|
|
|
|
/*
|
|
* Copyright (c) 2015, Wind River Systems, Inc.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
#ifndef _TEST_ASM_INLINE_GCC_H
|
|
#define _TEST_ASM_INLINE_GCC_H
|
|
|
|
#if !defined(__GNUC__)
|
|
#error test_asm_inline_gcc.h goes only with GCC
|
|
#endif
|
|
|
|
#if defined(CONFIG_X86)
|
|
static inline void timestamp_serialize(void)
|
|
{
|
|
__asm__ __volatile__ (/* serialize */
|
|
"xorl %%eax,%%eax;\n\t"
|
|
"cpuid;\n\t"
|
|
:
|
|
:
|
|
: "%eax", "%ebx", "%ecx", "%edx");
|
|
}
|
|
#elif defined(CONFIG_X86_64)
|
|
static inline void timestamp_serialize(void)
|
|
{
|
|
__asm__ volatile("xorq %%rax,%%rax; cpuid"
|
|
::: "rax", "rdx", "rbx", "rcx");
|
|
}
|
|
#elif defined(CONFIG_CPU_CORTEX_M)
|
|
#include <arch/arm/cortex_m/cmsis.h>
|
|
static inline void timestamp_serialize(void)
|
|
{
|
|
/* isb is avaialble in all Cortex-M */
|
|
__ISB();
|
|
}
|
|
#elif defined(CONFIG_CPU_ARCV2)
|
|
#define timestamp_serialize()
|
|
#elif defined(CONFIG_ARCH_POSIX)
|
|
#define timestamp_serialize()
|
|
#elif defined(CONFIG_XTENSA)
|
|
#define timestamp_serialize()
|
|
#elif defined(CONFIG_NIOS2)
|
|
#define timestamp_serialize()
|
|
#elif defined(CONFIG_RISCV32)
|
|
#define timestamp_serialize()
|
|
#else
|
|
#error implementation of timestamp_serialize() not provided for your CPU target
|
|
#endif
|
|
|
|
#endif /* _TEST_ASM_INLINE_GCC_H */
|