4344e27c26
Update reserved function names starting with one underscore, replacing them as follows: '_k_' with 'z_' '_K_' with 'Z_' '_handler_' with 'z_handl_' '_Cstart' with 'z_cstart' '_Swap' with 'z_swap' This renaming is done on both global and those static function names in kernel/include and include/. Other static function names in kernel/ are renamed by removing the leading underscore. Other function names not starting with any prefix listed above are renamed starting with a 'z_' or 'Z_' prefix. Function names starting with two or three leading underscores are not automatcally renamed since these names will collide with the variants with two or three leading underscores. Various generator scripts have also been updated as well as perf, linker and usb files. These are drivers/serial/uart_handlers.c include/linker/kobject-text.ld kernel/include/syscall_handler.h scripts/gen_kobject_list.py scripts/gen_syscall_header.py Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
127 lines
2.7 KiB
C
127 lines
2.7 KiB
C
/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Full C support initialization
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*
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*
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* Initialization of full C support: zero the .bss, copy the .data if XIP,
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* call z_cstart().
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*
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* Stack is available in this module, but not the global data/bss until their
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* initialization is performed.
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*/
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#include <zephyr/types.h>
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#include <toolchain.h>
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#include <linker/linker-defs.h>
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#include <arch/arc/v2/aux_regs.h>
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#include <kernel_structs.h>
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#include <kernel_internal.h>
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/* XXX - keep for future use in full-featured cache APIs */
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#if 0
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/**
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*
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* @brief Disable the i-cache if present
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*
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* For those ARC CPUs that have a i-cache present,
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* invalidate the i-cache and then disable it.
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*
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* @return N/A
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*/
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static void disable_icache(void)
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{
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unsigned int val;
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val = z_arc_v2_aux_reg_read(_ARC_V2_I_CACHE_BUILD);
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val &= 0xff; /* version field */
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if (val == 0) {
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return; /* skip if i-cache is not present */
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}
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z_arc_v2_aux_reg_write(_ARC_V2_IC_IVIC, 0);
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__asm__ __volatile__ ("nop");
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z_arc_v2_aux_reg_write(_ARC_V2_IC_CTRL, 1);
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}
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/**
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*
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* @brief Invalidate the data cache if present
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*
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* For those ARC CPUs that have a data cache present,
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* invalidate the data cache.
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*
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* @return N/A
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*/
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static void invalidate_dcache(void)
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{
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unsigned int val;
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val = z_arc_v2_aux_reg_read(_ARC_V2_D_CACHE_BUILD);
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val &= 0xff; /* version field */
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if (val == 0) {
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return; /* skip if d-cache is not present */
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}
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z_arc_v2_aux_reg_write(_ARC_V2_DC_IVDC, 1);
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}
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#endif
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/**
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*
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* @brief Adjust the vector table base
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*
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* Set the vector table base if the value found in the
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* _ARC_V2_IRQ_VECT_BASE auxiliary register is different from the
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* _VectorTable known by software. It is important to do this very early
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* so that exception vectors can be handled.
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*
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* @return N/A
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*/
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static void adjust_vector_table_base(void)
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{
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#ifdef CONFIG_ARC_HAS_SECURE
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#undef _ARC_V2_IRQ_VECT_BASE
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#define _ARC_V2_IRQ_VECT_BASE _ARC_V2_IRQ_VECT_BASE_S
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#endif
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extern struct vector_table _VectorTable;
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unsigned int vbr;
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/* if the compiled-in vector table is different
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* from the base address known by the ARC CPU,
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* set the vector base to the compiled-in address.
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*/
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vbr = z_arc_v2_aux_reg_read(_ARC_V2_IRQ_VECT_BASE);
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vbr &= 0xfffffc00;
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if (vbr != (unsigned int)&_VectorTable) {
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z_arc_v2_aux_reg_write(_ARC_V2_IRQ_VECT_BASE,
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(unsigned int)&_VectorTable);
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}
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}
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extern FUNC_NORETURN void z_cstart(void);
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/**
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*
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* @brief Prepare to and run C code
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*
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* This routine prepares for the execution of and runs C code.
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*
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* @return N/A
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*/
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void _PrepC(void)
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{
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_icache_setup();
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adjust_vector_table_base();
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z_bss_zero();
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z_data_copy();
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z_cstart();
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CODE_UNREACHABLE;
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}
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