Daniel Leung 7b31f93980 xtensa: enable XTENSA_HAL at SoC level ... This moves enabling XTENSA_HAL to the SoC definitions. As Xtensa SoCs are highly configurable, it is possible that the generic Xtensa HAL provided in the tree is not suitable. So only enable XTENSA_HAL only if the generic version can be used. Signed-off-by: Daniel Leung <daniel.leung@intel.com>		2020-04-08 13:10:35 -07:00
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arc	arch: arc: optimizations on irq lock/unlock in low level	2020-04-06 11:17:38 -07:00
arm	arch: arm: aarch32: rename z_arm_reserved to z_arm_exc_spurious	2020-04-07 09:57:12 -05:00
common	tests: benchmarks: use high-res counter for MEC1501 SoC	2020-03-31 19:52:21 -04:00
nios2	kernel: interrupt/idle stacks/threads as array	2020-03-16 23:17:36 +02:00
posix	tracing: move headers under include/tracing	2020-02-07 15:58:05 -05:00
riscv	RISCV compiler: Set mabi and march via Kconfig options	2020-04-06 21:54:07 -04:00
x86	arch: x86: Convert to new DT_INST macros	2020-03-26 03:29:23 -05:00
xtensa	xtensa: add calling entry point for multi-processing	2020-03-25 19:07:28 -04:00
CMakeLists.txt	arch: Simplify private header include path configuration.	2019-11-06 16:07:32 -08:00
Kconfig	xtensa: enable XTENSA_HAL at SoC level	2020-04-08 13:10:35 -07:00