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zephyr/dts/riscv
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Gerard Marull-Paretas 02aec77f77 dts: pwm: gd,gd32-pwm: add period to PWM cells 
Add the period cell to GD32 PWM compatible and update all boards
accordingly. A period of 20 ms (50 Hz) has been set for all PWM LEDs.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-04-07 09:35:22 +02:00
..
espressif drivers: wdt: esp32: code refactor to use hal calls 2022-02-21 19:40:17 -05:00
gigadevice dts: pwm: gd,gd32-pwm: add period to PWM cells 2022-04-07 09:35:22 +02:00
ite ITE drivers/interrupt_controller: add wuc interface 2022-03-21 16:35:03 -07:00
starfive boards: risc-v: add BeagleV Starlight JH7100 board support 2021-06-22 08:45:00 -04:00
andes_v5_ae350.dtsi dts: riscv: add DTS and related bindings of andes_ae350 soc 2021-08-30 13:40:14 -04:00
it8xxx2-alts-map.dtsi ITE: drivers/adc: implement ADC channels 13-16 2022-03-04 09:03:04 -06:00
it8xxx2.dtsi ITE drivers/timer: customize busy wait timer 2022-03-30 11:31:06 +02:00
microsemi-miv.dtsi
neorv32.dtsi dts: riscv: neorv32: add trng devicetree node 2021-10-26 17:53:15 -04:00
riscv32-fe310.dtsi soc: riscv: sifive-freedom: Get coreclk and peripheral clock from DTS. 2022-04-05 12:00:03 +02:00
riscv32-litex-vexriscv.dtsi dts: riscv32-litex-vexriscv.dtsi: drop 'spinalhdl' compatible 2021-08-17 17:51:57 -04:00
riscv64-fu540.dtsi soc: riscv: sifive-freedom: Get coreclk and peripheral clock from DTS. 2022-04-05 12:00:03 +02:00
riscv64-fu740.dtsi soc: riscv: sifive-freedom: Get coreclk and peripheral clock from DTS. 2022-04-05 12:00:03 +02:00
rv32m1_ri5cy.dtsi
rv32m1_zero_riscy.dtsi
rv32m1.dtsi riscv: rv32m1: Rework device_get_binding for pinmux 2021-02-15 08:32:41 -05:00
telink_b91.dtsi dts: riscv: telink_b91: replace pinmux by pinctrl 2022-02-21 19:41:44 -05:00
virt.dtsi soc/riscv: add the QEMU "RISC-V VirtIO board" 2021-01-15 13:06:33 -05:00