ed9cb841c3
Refactors all of the clock control drivers to use a shared driver class initialization priority configuration, CONFIG_CLOCK_CONTROL_INIT_PRIORITY, to allow configuring clock control drivers separately from other devices. This is similar to other driver classes like I2C and SPI. Most drivers previously used CONFIG_KERNEL_INIT_PRIORITY_OBJECTS or CONFIG_KERNEL_INIT_PRIORITY_DEVICE, therefore the default for this new option is the lower of the two, which means earlier initialization. The even lower defaults for STM32 and Arm Beetle are preserved by SoC-family level overrides. Signed-off-by: Maureen Helm <maureen.helm@intel.com>
58 lines
1.2 KiB
C
58 lines
1.2 KiB
C
/*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Copyright (C) 2021, Intel Corporation
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*
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*/
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#include <drivers/clock_control.h>
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#include <drivers/clock_control/clock_agilex_ll.h>
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#include <dt-bindings/clock/intel_socfpga_clock.h>
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#include <logging/log.h>
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#include <soc.h>
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LOG_MODULE_REGISTER(clock_control, CONFIG_CLOCK_CONTROL_LOG_LEVEL);
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static int clk_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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LOG_INF("Intel Clock driver initialized");
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return 0;
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}
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static int clk_get_rate(const struct device *dev,
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clock_control_subsys_t sub_system,
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uint32_t *rate)
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{
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ARG_UNUSED(dev);
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struct clock_attr *attr = (struct clock_attr *)(sub_system);
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switch (attr->clock_id) {
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case INTEL_SOCFPGA_CLOCK_MPU:
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*rate = get_mpu_clk();
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break;
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case INTEL_SOCFPGA_CLOCK_WDT:
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*rate = get_wdt_clk();
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break;
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case INTEL_SOCFPGA_CLOCK_UART:
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*rate = get_uart_clk();
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break;
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case INTEL_SOCFPGA_CLOCK_MMC:
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*rate = get_mmc_clk();
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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static const struct clock_control_driver_api clk_api = {
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.get_rate = clk_get_rate
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};
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DEVICE_DT_DEFINE(DT_NODELABEL(clock), clk_init, NULL, NULL, NULL,
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PRE_KERNEL_1, CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
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&clk_api);
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