1e9ada4eb9
Intel's adsp needs to set, at a minimum, a clocking bit before the driver can initialize the designware dma controller. In many ways it is the designware dmac IP but with additional registers and functionality added on top of it. So the code structure here follows how the hardware appears to be designed, layered on top of the designware driver. Signed-off-by: Tom Burdick <thomas.burdick@intel.com> |
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| .. | ||
| altr,msgdma.yaml | ||
| arm,dma-pl330.yaml | ||
| atmel,sam0-dmac.yaml | ||
| atmel,sam-xdmac.yaml | ||
| brcm,iproc-pax-dma-v1.yaml | ||
| brcm,iproc-pax-dma-v2.yaml | ||
| dma-controller.yaml | ||
| dmamux-controller.yaml | ||
| intel,cavs-gpdma.yaml | ||
| nxp,lpc-dma.yaml | ||
| nxp,mcux-edma.yaml | ||
| snps,designware-dma.yaml | ||
| st,stm32-dma-v1.yaml | ||
| st,stm32-dma-v2.yaml | ||
| st,stm32-dma-v2bis.yaml | ||
| st,stm32-dma.yaml | ||
| st,stm32-dmamux.yaml | ||