27a59ec9d5
Intel Audio DSPs have "IPC" interrupt delivery and shared memory window hardware. The Sound Open Firmware project has historically used the combination of these to implement a bidirectional message-passing interface. As it happens, this protocol is an excellent fit for Zephyr's somewhat geriatric but still useful IPM interface. This implements a SOF-protocol-compatible transport that will hopefully prove a bit more futureproof for non-Intel SOF architectures. It is a software-only device, built on top of the underlying SOC APIs for the SRAM windows (in cavs-shim) and IPC (cavs_ipc). Note that SOF actually has two protocol variants (ipc3 and ipc4): in both, the command header (passed as the "id" parameter in IPM) is sent via the hardware doorbell register. But in ipc4, the second hardware scratch register is used to transmit the first four bytes of the command before involving the SRAM window (in ipc3, it's ignored). Both modes are supported by this driver, set IPM_CAVS_HOST_REGWORD to choose the "ipc4" variant. Finally: note that the memory layout for the windows in question is inherited from SOF, and for compatibility (with both SOF and with the offsets used by the host!) these can't be changed without major surgery. They're defined in kconfig, but should be treated as read-only until we get a chance to rework the way Zephyr does its SRAM window management (and probably in concert with the host drivers). Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
187 lines
4.4 KiB
Plaintext
187 lines
4.4 KiB
Plaintext
# SPDX-License-Identifier: Apache-2.0
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menuconfig IPM
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bool "IPM drivers"
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help
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Include interrupt-based inter-processor mailboxes
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drivers in system configuration
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if IPM
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config IPM_MCUX
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bool "MCUX IPM driver"
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depends on HAS_MCUX
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help
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Driver for MCUX mailbox
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config IPM_IMX
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bool "IMX IPM driver"
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depends on HAS_IMX_HAL
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help
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Driver for NXP i.MX messaging unit
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config IPM_IMX_REV2
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bool "IMX IPM driver (rev 2)"
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depends on HAS_MCUX
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depends on !IPM_IMX
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help
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Rev 2 driver for NXP i.MX messaging unit (MCUX-based)
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choice
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prompt "IMX IPM max data size"
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default IPM_IMX_MAX_DATA_SIZE_16
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depends on IPM_IMX || IPM_IMX_REV2
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help
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Select maximum message size for NXP i.MX messaging unit.
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config IPM_IMX_MAX_DATA_SIZE_4
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bool "4 bytes"
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help
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There will be four message types with ids 0, 1, 2 or 3
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and a maximum size of 4 bytes each.
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config IPM_IMX_MAX_DATA_SIZE_8
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bool "8 bytes"
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help
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There will be two message types with ids 0 or 1
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and a maximum size of 8 bytes each.
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config IPM_IMX_MAX_DATA_SIZE_16
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bool "16 bytes"
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help
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There will be a single message type with id 0
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and a maximum size of 16 bytes.
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endchoice
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config IPM_IMX_MAX_DATA_SIZE
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int
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range 4 16
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default 4 if IPM_IMX_MAX_DATA_SIZE_4
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default 8 if IPM_IMX_MAX_DATA_SIZE_8
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default 16 if IPM_IMX_MAX_DATA_SIZE_16
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depends on IPM_IMX || IPM_IMX_REV2
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config IPM_IMX_MAX_ID_VAL
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int
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range 0 3
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default 3 if IPM_IMX_MAX_DATA_SIZE_4
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default 1 if IPM_IMX_MAX_DATA_SIZE_8
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default 0 if IPM_IMX_MAX_DATA_SIZE_16
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depends on IPM_IMX || IPM_IMX_REV2
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config IPM_MHU
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bool "IPM MHU driver"
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help
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Driver for SSE 200 MHU (Message Handling Unit)
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config IPM_NRFX
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bool "IPM NRF driver"
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depends on HAS_HW_NRF_IPC
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select NRFX_IPC
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help
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Driver for Nordic nRF messaging unit, based
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on nRF IPC peripheral HW.
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config IPM_NRF_SINGLE_INSTANCE
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bool "Single instance of IPM device"
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help
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Enable this option if the IPM device should have
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a single instance, instead of one per IPC
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message channel.
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source "drivers/ipm/Kconfig.nrfx"
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config IPM_STM32_IPCC
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bool "STM32 IPCC controller"
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select USE_STM32_LL_IPCC
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help
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Driver for stm32 IPCC mailboxes
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config IPM_STM32_IPCC_PROCID
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int "STM32 IPCC Processor ID"
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default 2
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range 1 2
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depends on IPM_STM32_IPCC
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help
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use to define the Processor ID for IPCC access
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config IPM_CAVS_IDC
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bool "CAVS DSP Intra-DSP Communication (IDC) driver"
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depends on IPM && CAVS_ICTL
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default y if MP_NUM_CPUS > 1 && SMP
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help
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Driver for the Intra-DSP Communication (IDC) channel for
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cross SoC communications.
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config IPM_STM32_HSEM
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bool "STM32 HSEM controller"
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depends on STM32H7_DUAL_CORE
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help
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Driver for stm32 HSEM mailbox
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config IPM_STM32_HSEM_CPU
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int "HSEM CPU ID"
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default 1 if "$(dt_nodelabel_enabled,cpu0)"
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default 2 if "$(dt_nodelabel_enabled,cpu1)"
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range 1 2
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depends on IPM_STM32_HSEM
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help
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use to define the CPU ID used by HSEM
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config IPM_CALLBACK_ASYNC
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bool "Deliver callbacks asynchronously"
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default y if IPM_CAVS_HOST
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help
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When selected, the driver supports "asynchronous" command
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delivery. Commands will stay active after the ISR returns,
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until the application expressly "completes" the command
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later.
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config IPM_CAVS_HOST
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bool "cAVS DSP/host communication"
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select CAVS_IPC
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help
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Driver for host/DSP communication on intel_adsp devices
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if IPM_CAVS_HOST
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config IPM_CAVS_HOST_INBOX_OFFSET
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hex "Byte offset of cAVS inbox window"
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depends on CAVS_IPC
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default 0x6000
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help
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Location of the host-writable inbox window within the
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HP_SRAM_RESERVE region. This location must be synchronized
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with host driver and SOF source code (must match
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SRAM_INBOX_BASE). Be careful.
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config IPM_CAVS_HOST_OUTBOX_OFFSET
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hex "Byte offset of cAVS outbox memory"
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depends on CAVS_IPC
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default 0x1000
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help
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Location of the "outbox" region for SOF IPC3/4 message
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within the pre-existing window 0 (this is not the same as
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the HP_SRAM_RESERVE region used for INBOX_OFFSET). This
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location must be synchronized with host driver and SOF
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source code (where it must equal SRAM_SW_REG_SIZE). Be
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careful.
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config IPM_CAVS_HOST_REGWORD
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bool "Store first 4 bytes in IPC register"
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depends on CAVS_IPC
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depends on !SOC_SERIES_INTEL_CAVS_V15
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help
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Protocol variant. When true, the first four bytes of a
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message are passed in the cAVS IDR/TDR register pair instead
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of in the SRAM window. Only available on cAVS 1.8+.
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endif # IPM_CAVS_HOST
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module = IPM
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module-str = ipm
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source "subsys/logging/Kconfig.template.log_config"
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endif #IPM
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